US2005072121A1PendingUtilityA1

Method and system for shipping semiconductor wafers

Assignee: TEXAS INSTRUMENTS INCPriority: Oct 6, 2003Filed: Oct 6, 2003Published: Apr 7, 2005
Est. expiryOct 6, 2023(expired)· nominal 20-yr term from priority
H10P 72/1912H10P 72/18
39
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Claims

Abstract

According to one embodiment of the invention, an apparatus includes a plurality of coin stacks of semiconductor wafers. Each coin stack includes a plurality of semiconductor wafers separated from an adjacent wafer by a wafer separator disposed within a coin stack carrier. The apparatus also includes a shipping box having the plurality of coin stacks disposed therein such that each of the wafers in each of the coin stack carriers has a vertical orientation.

Claims

exact text as granted — not AI-modified
1 . A method for shipping semiconductor wafers each having metallization subject to damage comprising: 
 providing a plurality of coin stacks, each coin stack comprising a plurality of semiconductor wafers separated from adjacent wafers by a ring-shaped wafer separator formed from plastic and disposed within a coin stack carrier, each semiconductor wafer having a plurality of interconnection conductor material portions, each coin stack further comprising first and second protection barriers formed from foam; and    positioning each of the plurality of coin stack carriers in a shipping box such that each of the wafers in each of the coin stack carriers has a vertical orientation, the shipping box having a vertical arrow disposed thereon to indicate the orientation the shipping box should be maintained to maintain the wafers in a vertical orientation.    
   
   
       2 . The method of  claim 1 , wherein the plurality of interconnection conductor material portions comprise a plurality of solder bumps.  
   
   
       3 . The method of  claim 1 , wherein the plurality of interconnection conductor material portions comprise a plurality of flip chip bumps.  
   
   
       4 . The method of  claim 1 , wherein the plurality of interconnection conductor material portions comprise a plurality of bond pads.  
   
   
       5 . The method of  claim 2 , wherein the wafer separator comprises: 
 a first surface;    a first recessed portion formed in the wafer separator, the first recessed portion having an outer perimeter shape corresponding to an outer perimeter shape of the wafers, and the first recessed portion having a first depth from the first surface; and    a second recessed portion formed in the wafer separator and located at least partially within the first recessed portion, the second recessed portion having a bottom surface at a second depth from the first surface, wherein the second depth is greater than the first depth.    
   
   
       6 . A method for shipping semiconductor wafers comprising: 
 providing a plurality of coin stacks, each coin stack comprising a plurality of semiconductor wafers each separated from an adjacent wafer by a wafer separator and also including first and second protection barriers disposed at opposite ends of the coin stack;    positioning each of the plurality of coin stack carriers in a shipping box such that each of the wafers in each of the coin stack carriers has a vertical orientation; and    providing visual indicia on the shipping box of the orientation in which the shipping box should be maintained to maintain the wafers in a vertical orientation.    
   
   
       7 . The method of  claim 6 , wherein the plurality of wafer separators are ring-shaped.  
   
   
       8 . The method of  claim 6 , wherein the first and second protection barriers are formed from foam.  
   
   
       9 . The method of  claim 6 , wherein the coin stack carrier is formed from plastic.  
   
   
       10 . The method of  claim 6 , wherein the visual indicia comprises an arrow pointing upwards.  
   
   
       11 . The method of  claim 6 , wherein each of the semiconductor wafers comprises a plurality of interconnection conductor material portions.  
   
   
       12 . The method of  claim 11 , wherein the plurality of interconnection conductor material portions comprise a plurality of solder bumps.  
   
   
       13 . The method of  claim 11 , wherein the plurality of interconnection conductor material portions comprise a plurality of flip chip bumps.  
   
   
       14 . The method of  claim 11 , wherein the plurality of interconnection conductor material portions comprise a plurality of bond pads.  
   
   
       15 . The method of  claim 11 , wherein the wafer separator comprises: 
 a first surface;    a first recessed portion formed in the wafer separator, the first recessed portion having an outer perimeter shape corresponding to an outer perimeter shape of the wafers, and the first recessed portion having a first depth from the first surface; and    a second recessed portion formed in the wafer separator and located at least partially within the first recessed portion, the second recessed portion having a second surface at a second depth from the first surface, wherein the second depth is greater than the first depth, and wherein the second depth minus the first depth is greater than a maximum height of the interconnection conductor material portions.    
   
   
       16 . The method of  claim 6 , wherein the visual indication comprises writing.  
   
   
       17 . An apparatus comprising: 
 a plurality of coin stacks each comprising a plurality of semiconductor wafers disposed within a coin stack carrier, each coin stack comprising a plurality of semiconductor wafers separated from an adjacent wafer by a wafer separator; and    a shipping box having the plurality of coin stacks disposed therein such that each of the wafers in each of the coin stack carriers has a vertical orientation.    
   
   
       18 . The apparatus of  claim 17 , wherein the shipping box comprises visual indicia formed therein of the orientation in which the shipping box should be maintained to maintain the wafers in a vertical orientation.  
   
   
       19 . The apparatus of  claim 17 , wherein the visual indicia comprises an arrow pointing upwards.  
   
   
       20 . The apparatus of  claim 17 , wherein each of the semiconductor wafers comprises a plurality of flip chip bumps.

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