System resource router

Abstract

A system resource router for SOC applications is described. Data-transfer initiators coupled to the router via one of a plurality of channel socket connections ( 144, 146, 148, 150, 152, 154 ) alternatively couple to internal M-channel buses ( 162, 164, 166 ) using transfer switches ( 168, 170, 172 ). Each internal M-channel bus connects to an external M-channel bus ( 114, 116, 118 ) populated by one or more transaction targets using an M-channel controller ( 156, 158, 160 ). The channel sockets, at least some of the data-transfer initiators, the internal M-channel buses, the external M-channel buses, and at least some of the transaction targets are all contained upon a single integrated circuit (IC) SOC device. Split reads and full duplex transactions are supported. Transactions can occur at different clock frequencies and bandwidths.

1 . A system resource router within a system-on-chip (SOC) device, comprising 
 at least two channel sockets, wherein each said channel socket provides for protocol-based connections to data-transfer initiators;    first and second internal M-channel buses that alternately connect to at least one of said channel sockets using a transfer switch; and    a first M-channel controller that connects said first internal M-channel bus to a first external M-channel bus populated by one or more transaction targets; and    a second M-channel controller that connects said second internal M-channel bus to a second external M-channel bus populated by one or more transaction targets;    wherein said transfer switch operatively couples a data-transfer initiator connected to said channel socket to a transaction target using either said first internal M-channel bus, said first M-channel controller, and said first external M-channel bus, or said second internal M-channel bus, said second M-channel controller, and said second external M-channel bus; and    wherein said channel sockets, said data-transfer initiators, said first and second internal M-channel buses, said first and second external M-channel buses, and at least some of said one or more transaction targets are all contained upon a single integrated circuit (IC) device.    
   
   
       2 . A resource routing system, comprising 
 at least two channel sockets, wherein each said channel socket provides for protocol-based connections to data-transfer initiators;    first and second internal M-channel buses that alternately connect to at least one of said channel sockets using a transfer switch; and    a first M-channel controller that connects said first internal M-channel bus to a first external M-channel bus populated by one or more transaction targets; and    a second M-channel controller that connects said second internal M-channel bus to a second external M-channel bus populated by one or more transaction targets;    wherein said transfer switch operatively couples a data-transfer initiator connected to said channel socket to a transaction target using either said first internal M-channel bus, said first M-channel controller, and said first external M-channel bus, or said second internal M-channel bus, said second M-channel controller, and said second external M-channel bus; and    wherein said channel sockets, said data-transfer initiators, said first and second internal M-channel buses, said first and second external M-channel buses, and at least some of said one or more transaction targets are all contained upon a single integrated circuit (IC) device.    
   
   
       3 . A method that makes a system resource router on a system-on-chip (SOC) device, comprising 
 providing at least two channel sockets, wherein each said channel socket provides for protocol-based connections to data-transfer initiators;    providing first and second internal M-channel buses that alternately connect to at least one of said channel sockets using a transfer switch; and    providing a first M-channel controller that connects said first internal M-channel bus to a first external M-channel bus populated by one or more transaction targets; and    providing a second M-channel controller that connects said second internal M-channel bus to a second external M-channel bus populated by one or more transaction targets;    wherein said transfer switch operatively couples a data-transfer initiator connected to said channel socket to a transaction target using either said first internal M-channel bus, said first M-channel controller, and said first external M-channel bus, or said second internal M-channel bus, said second M-channel controller, and said second external M-channel bus; and    wherein said channel sockets, said data-transfer initiators, said first and second internal M-channel buses, said first and second external M-channel buses, and at least some of said one or more transaction targets are all contained upon a single integrated circuit (IC) device.    
   
   
       4 . A method that uses a system resource router within a system-on-chip (SOC) device, comprising 
 operatively coupling a data-transfer initiator to one of at least two channel sockets, that provides for protocol-based connections;    operatively coupling said data-transfer initiator to one of first and second internal M-channel buses using a transfer switch that provides alternative connections from said one of at least two channel sockets to said first and second internal M-channel buses; and    operatively coupling to a transaction target through one of the following: a first M-channel controller that connects said first internal M-channel bus to a first external M-channel bus populated by one or more transaction targets, or    a second M-channel controller that connects said second internal M-channel bus to a second external M-channel bus populated by one or more transaction targets;    wherein said channel sockets, said data-transfer initiator, said first and second internal M-channel buses, said first and second external M-channel buses, and at least some of said one or more transaction targets are all contained upon a single integrated circuit (IC) device.    
   
   
       5 . A dependent claim according to  claim 1 ,  2 ,  3 , or  4  wherein either said first or said second internal M-channel bus further comprises a synchronous bus, and said transfer switch couples said data-transfer initiator to said synchronous bus through a synching FIFO.  
   
   
       6 . A dependent claim according to  claim 5 , wherein said data-transfer initiator, said synchronous bus, and said transaction target are all running at different clock frequencies.  
   
   
       7 . A dependent claim according to  claim 1 ,  2 ,  3 , or  4 , wherein one of said first and second internal M-channel buses further comprises an embedded memory channel that provides a point-to-point connection to internal or external memory.  
   
   
       8 . A dependent claim according to  claim 1 ,  2 ,  3 , or  4  wherein said channel sockets and said M-channel controllers convert a transaction from a first group of one or more bursts having a first bandwidth to a second group of one or more bursts having a second bandwidth.  
   
   
       9 . A dependent claim according to  claim 1 ,  2 ,  3 , or  4  wherein two transactions between two data-transfer initiators and two targets occurring over one of said first and second internal M-channel buses comprise one of the following: split read transactions, wherein read transfers are returned across said internal M-channel buses in a different order than originally requested, or full duplex transactions, where one transaction is a read burst from one data-transfer initiator to a target and the other transaction is a simultaneous write burst from a second data-transfer initiator to a second target.