Raised-lines overlay semiconductor targets and method of making the same

Abstract

The present invention includes a residue-free overlay target, as well as a method of forming a residue-free overlay target. The residue-free overlay target of the present invention is defined by trenches or pads including a series of raised lines. The raised lines included in the overlay target of the present invention substantially eliminate any surface topography, such as depressions, at the top surface of overlying material layers and, thereby, prevent accumulation of process residue which may obscure the overlay target and inhibit further processing. The method of the present invention may be accomplished and modified using process technology known in the semiconductor fabrication art and includes providing a semiconductor substrate, depositing a resist layer, patterning the resist, and executing a wet or dry etch to create at least one overlay target according to the present invention.

1 . A method for forming an overlay target in a wafer, the method comprising: 
 patterning a resist layer deposited on a portion of the wafer to include a pattern for an overlay target including a series of raised lines;    etching the substrate to form the overlay target; and    depositing a second layer of material substantially over a portion of the substrate for allowing registration of the wafer using the series of raised lines of the overlay target.    
   
   
       2 . An overlay target on a wafer comprising: 
 a plurality of raised lines in the wafer covered by a layer of material forming a target for allowing registration of the wafer using the series of raised lines of the overlay target.    
   
   
       3 . A method for forming an overlay target in a wafer for use in a semiconductor process manufacturing process, the method comprising: 
 patterning a resist layer deposited on a portion of the wafer to include a pattern for an overlay target including a series of raised lines;    etching the substrate to form the overlay target; and    depositing a second layer of material substantially over a portion of the substrate for allowing registration of the wafer using the series of raised lines of the overlay target.    
   
   
       4 . An overlay target on a wafer for use in a semiconductor manufacturing process comprising: 
 a plurality of raised lines in the wafer covered by a layer of material forming a target for allowing registration of the wafer using the series of raised lines of the overlay target.    
   
   
       5 . A method for a wafer for forming an overlay target thereon, the method comprising: 
 patterning a resist layer deposited on a portion of the wafer to include a pattern for an overlay target including a series of raised lines;    etching the substrate to form the overlay target; and    depositing a second layer of material substantially over a portion of the substrate for allowing registration of the wafer using the series of raised lines of the overlay target.    
   
   
       6 . An overlay target on a formed on a wafer in a manufacturing process comprising: 
 a plurality of raised lines in the wafer covered by a layer of material forming a target for allowing registration of the wafer using the series of raised lines of the overlay target.