Method and apparatus for processing data in a reconfigurable manner

Abstract

Processor architecture adapts to input data. With each incoming data, the processor adapts in real-time. The structure of the processors is adapted by configuring a reconfigurable logic element. Reconfiguration occurs based on a portion of the input data to select a configuration map. The configuration map parallel loads the reconfigurable logic element, thus avoiding latency associated with reconfiguration.

1 . A method for processing data in a reconfigurable manner comprising: 
 receiving input data;    selecting a logic configuration according to the input data; and    processing the input data using the selected logic configuration.    
   
   
       2 . The method of  claim 1  wherein receiving input data comprises: 
 receiving a plurality of data;    determining a type of the plurality of data; and    generating a logic selection indicator according to the determined type of the plurality of input data.    
   
   
       3 . The method of  claim 1  wherein selecting a logic configuration comprises: 
 selecting a configuration map according to a portion of the input data; and    creating a logic function in accordance with the selected configuration map.    
   
   
       4 . The method of  claim 3  wherein selecting a configuration map comprises selecting a configuration map for at least one of an addressing unit, an instruction decoder, an instruction sequencer and an arithmetic unit.  
   
   
       5 . The method of  claim 1  wherein selecting a logic configuration comprises: 
 creating a logic function in accordance with a first configuration map during a first data period; and    creating a second logic function in accordance with a second configuration map during a second data period.    
   
   
       6 . The method of  claim 1  wherein selecting a logic configuration comprises: 
 generating a parallel configuration word according to the input data;    configuring a plurality of logic elements substantially in one data period using the parallel configuration word.    
   
   
       7 . The method of  claim 1  wherein processing the input data comprises: 
 configuring a first logic element according to a first input data;    processing the first input data using the first logic element;    configuring a second logic element according to the first input data substantially while reconfiguring the first logic element according to a subsequent input data; and    processing the once-processed first input data using the second logic element substantially while processing the subsequent input data using the reconfigured first logic element.    
   
   
       8 . The method of  claim 1  further comprising: 
 determining the amount of power required to process the input data using the selected logic configuration; and    selecting a new logic configuration when the amount of power required exceeds a pre-established threshold.    
   
   
       9 . A data processing unit comprising: 
 input unit capable of receiving input data;    reconfigurable logic circuit capable of processing the input data; and    configuration circuit capable of configuring the reconfigurable logic circuit according to a portion of the input data.    
   
   
       10 . The data processing unit of  claim 9  wherein the configuration circuit comprises: 
 data monitor capable of determining a type for the input data; and    configuration memory capable of storing a plurality of configuration maps, wherein a configuration map is selected according to a portion the determined type.    
   
   
       11 . The data processing unit of  claim 9  wherein the configuration circuit comprises: 
 data monitor capable of generating a configuration selection signal according to a portion of the input data; and    configuration memory capable of storing a plurality of configuration maps, wherein a configuration map is selected according to the configuration selection signal.    
   
   
       12 . The data processing unit of  claim 9  wherein the configuration circuit includes a configuration map for at least one of an addressing unit, an instruction decoder, an instruction sequencer and an arithmetic unit.  
   
   
       13 . The data processing unit of  claim 9  wherein the configuration circuit comprises: 
 active configuration unit capable of configuring reconfigurable logic circuit during a first data period; and    loading configuration unit capable of receiving a new configuration map while the active configuration unit is configuring the reconfigurable logic circuit and is further capable of configuring reconfigurable logic circuit during a second data period.    
   
   
       14 . The data processing unit of  claim 9  wherein the configuration circuit comprises a configuration memory that generates a parallel configuration word.  
   
   
       15 . The data processing unit of  claim 9  wherein the reconfigurable logic circuit comprises: 
 first logic element capable of processing a first input data according to a first configuration; and    second logic element capable of processing a once-processed first data received from the first logic element according to a first configuration while the first logic element processes a subsequent data according to a subsequent configuration.    
   
   
       16 . The data processing unit of  claim 9  further comprising power monitor capable of determining the power consumed by the reconfigurable logic circuit wherein the configuration circuit is capable of selecting a different configuration map when the determined power exceeds a pre-established threshold.  
   
   
       17 . A data processing unit comprising: 
 input unit capable of receiving input data;    data storage unit capable of storing at least one of the input data and an intermediate result;    reconfigurable logic circuit capable of processing the input data and an intermediate result; and    configuration circuit capable of configuring the reconfigurable logic circuit according to at least one of a portion of the input data and a portion of an intermediate result.    
   
   
       18 . The data processing unit of  claim 17  wherein the configuration circuit comprises: 
 data monitor capable of determining a type for the input data; and    configuration memory capable of storing a plurality of configuration maps, wherein a configuration map is selected according to a portion the determined type.    
   
   
       19 . The data processing unit of  claim 17  wherein the configuration circuit comprises: 
 data monitor capable of generating a configuration selection signal according to a portion of the input data; and    configuration memory capable of storing a plurality of configuration maps, wherein a configuration map is selected according to the configuration selection signal.    
   
   
       20 . The data processing unit of  claim 17  wherein the configuration circuit includes a reconfigurable logic circuit comprising multiple function specific sub-circuits wherein each sub-circuit comprises at least one of a general purpose specific logic element and a function specific logic element that is optimized to configure the sub-circuit.  
   
   
       21 . The data processing unit of  claim 20  wherein the reconfigurable logic circuit is capable of selecting from one or more fixed configurations as an active circuit configuration while one or more programmable configurations is being loaded.  
   
   
       22 . The data processing unit of  claim 17  wherein the configuration circuit comprises: 
 active configuration unit capable of configuring reconfigurable logic circuit during a first data period; and    loading configuration unit capable of receiving a new configuration map while the active configuration unit is configuring the reconfigurable logic circuit and is further capable of configuring reconfigurable logic circuit during a second data period.    
   
   
       23 . The data processing unit of  claim 17  wherein the configuration circuit comprises a configuration memory that generates a parallel configuration word.  
   
   
       24 . The data processing unit of  claim 17  wherein the configuration circuit comprises: 
 process sequencing mechanism capable of choosing a sequence of states;    configuration circuit capable of configuring the reconfigurable logic circuit according to a chosen state.    
   
   
       25 . The data processing unit of  claim 17  wherein the reconfigurable logic circuit comprises: 
 first logic element capable of processing a first input data according to a first configuration; and    second logic element capable of processing a once-processed first data received from the first logic element according to a first configuration while the first logic element processes a subsequent data according to a subsequent configuration.    
   
   
       26 . The data processing unit of  claim 17  further comprising power monitor capable of determining the power consumed by the reconfigurable logic circuit wherein the configuration circuit is capable of selecting a different configuration map when the determined power exceeds a pre-established threshold.