Interrupt disabling apparatus, system, and method

Abstract

An interrupt processing apparatus, system, and article including a machine-accessible medium, along with a method of processing interrupts, optimize interrupt-handling by combining the activities of acknowledging and disabling the interrupt. In one embodiment, the apparatus may include an interrupt cause register coupled to an interrupt disabling register and an interrupt mask register. The system may include a processor coupled to an interrupt cause register using a bus, along with an interrupt disabling register coupled to an interrupt mask register and the interrupt disabling register. The method may include reading an interrupt cause register in response to receiving an interrupt, and transferring a mask value stored in an interrupt disabling register directly to an interrupt mask register so as to disable receiving further interrupts from the interrupt source.

1 . An apparatus, comprising: 
 a cause register;    a disabling register to couple to the cause register; and    a mask register to couple to the disabling register.    
   
   
       2 . The apparatus of  claim 1 , wherein the cause register, the disabling register, and the mask register are included in a single monolithic memory circuit.  
   
   
       3 . The apparatus of  claim 1 , wherein the cause register, the disabling register, and the mask register are included in a single programmable interrupt controller.  
   
   
       4 . The apparatus of  claim 1 , further comprising: 
 an arithmetic logic unit to couple to the mask register.    
   
   
       5 . The apparatus of  claim 1 , further comprising: 
 an override register to couple to the mask register.    
   
   
       6 . The apparatus of  claim 1 , further comprising: 
 a device driver to couple to the disabling register.    
   
   
       7 . A system, comprising: 
 a bus;    an interrupt cause register to couple to the bus;    an interrupt disabling register to couple to the interrupt cause register; and    a mask register to couple to the interrupt disabling register.    
   
   
       8 . The system of  claim 7 , further comprising: 
 a device capable of generating an interrupt to couple to the bus.    
   
   
       9 . The system of  claim 8 , wherein the device comprises a network adapter.  
   
   
       10 . The system of  claim 8 , wherein the device comprises a graphics display controller.  
   
   
       11 . The system of  claim 8 , wherein the device comprises a storage device.  
   
   
       12 . The system of  claim 7 , wherein the bus comprises a peripheral component interconnect (PCI) bus.  
   
   
       13 . The system of  claim 7 , wherein reading the interrupt cause register results in transferring a value stored in the interrupt disabling register to the interrupt mask register.  
   
   
       14 . A method, comprising: 
 reading an interrupt cause register in response to receiving an interrupt; and    transferring a value stored in an interrupt disabling register corresponding to a source of the interrupt to an interrupt mask register to disable receiving further interrupts from the source of the interrupt.    
   
   
       15 . The method of  claim 14 , further comprising: 
 generating the interrupt.    
   
   
       16 . The method of  claim 14 , further comprising: 
 executing an interrupt service routine to acknowledge the interrupt.    
   
   
       17 . The method of  claim 14 , further comprising: 
 writing an override value to an interrupt disabling override register; and    transferring the override value to the interrupt mask register to enable receiving further interrupts from the source of the interrupt.    
   
   
       18 . An article comprising a machine-accessible medium having associated instructions, wherein the instructions, when accessed, result in a machine performing: 
 reading an interrupt cause register in response to receiving an interrupt; and    transferring a value stored in an interrupt disabling register corresponding to a source of the interrupt to an interrupt mask register to disable receiving further interrupts from the source of the interrupt.    
   
   
       19 . The article of  claim 18 , wherein the instructions, when accessed, result in the machine performing: 
 writing a message signaling an interrupt to a memory location.    
   
   
       20 . The article of  claim 18 , wherein the value is transferred without accessing a bus.  
   
   
       21 . The article of  claim 18 , wherein the instructions, when accessed, result in the machine performing: 
 generating a multiplicity of interrupts using the source of the interrupt;    repeatedly reading the interrupt cause register in response to receiving the multiplicity of interrupts; and    repeatedly transferring the value stored in the interrupt disabling register corresponding to the source of the interrupt to the interrupt mask register.