Formation of low resistance via contacts in interconnect structures

Abstract

A method of fabricating an interconnect structure including the steps of: forming a porous or dense low k dielectric layer on a substrate; forming single or dual damascene etched openings in the low k dielectric; placing the substrate in a process chamber on a cold chuck at a temperature about −200° C. to about 25° C.; adding to the process chamber a condensable cleaning agent (CCA) to condense a layer of CCA within the etched openings on the substrate; and activating at a temperature about −200° C. to about 25° C. Also provided is an interconnect structure having a substrate, a conductive material disposed on the substrate, a porous or dense low k dielectric layer disposed on the conductive material, wherein the low k dielectric layer has a single or dual damascene etched openings that expose a surface of the conductive material, and metallic lines and vias etched onto the low k dielectric layer; wherein the exposed conductive material has been treated with a CCA and activated in the cold to remove oxide, oxygen and carbon containing residues from the surface of the conductive material.

1 - 40 . (canceled)  
     
     
         41 . An interconnect structure comprising: 
 a substrate;    a conductive material disposed on said substrate;    a porous or dense low k dielectric layer disposed on said conductive material, wherein said low k dielectric layer has a single or dual damascene etched openings that expose a surface of said conductive material; and    metallic lines and vias etched onto said low k dielectric layer;    wherein said exposed surface of said conductive material in said etched openings has been treated with a condensable cleaning agent (CAA) and activated at a temperature about −200° C. to about 25° C. to remove oxide, oxygen and carbon containing residues from said surface of said conductive material.    
     
     
         42 . The interconnect structure of  claim 41 , further comprising a liner material lining said metallic lines and vias.  
     
     
         43 . The interconnect structure of  claim 42 , wherein said liner material is selected from the group consisting of: TiN, TaN, Ta, WN, W, TaSiN, TiSiN, WCN, Ru and a mixture thereof.  
     
     
         44 . The interconnect structure of  claim 41 , wherein said porous or dense low k dielectric is selected from the group consisting of: 
 silicon-containing material formed from one or more of Si, C, O, F and H, PE CVD materials having a composition Si, C, O, and H, a fluorosilicate glass (FSG), C doped oxide, F doped oxide and alloys of Si, C, O and H.    
     
     
         45 . The interconnect structure of  claim 41 , wherein said interconnect structure is placed in a first process chamber on a cold chuck to condense a layer of condensable cleaning agent within said etched openings on said substrate and thereafter activated in a second process chamber on a cluster tool.  
     
     
         46 . The interconnect structure of  claim 41 , wherein said metallic lines and vias are filled with Cu.  
     
     
         47 . The interconnect structure of  claim 41 , wherein said conductive material disposed on said substrate is selected from the group consisting of: W, Cu, Al, Ag, Au and alloys thereof.  
     
     
         48 . The interconnect structure of  claim 47 , wherein said conductive material is Cu.