Semiconductor device and method for manufacturing the same

Abstract

A semiconductor device and a method for manufacturing the same are provided having a high breakdown voltage transistor and a low breakdown voltage transistor with different driving voltages in a common substrate. The semiconductor device includes: a semiconductor substrate of a first conductivity type; a first well of a second conductivity type formed in the semiconductor substrate; a second well of the first conductivity type formed within the first well; a third well of the second conductivity type formed within the first well; a low breakdown voltage transistor of the second conductivity type formed at the second well; a low breakdown voltage transistor of the first conductivity type formed at the third well; and a high breakdown voltage transistor of the first conductivity type formed at the first well. The second well and the third well have an impurity concentration higher than an impurity concentration of the first well.

1 . A method for manufacturing a semiconductor device, the method comprising: 
 (a) forming a first well of a second conductivity type in a semiconductor substrate of a first conductivity type;    (b) introducing impurities of the first and second conductivity types by implanting ions in specified regions of the first well to form a first impurity layer and a second impurity layer; and    (c) diffusing the impurities in the first impurity layer and the second impurity layer by heat treating to form a second well of the first conductivity type and a third well of the second conductivity type in the first well.    
   
   
       2 . The method for manufacturing a semiconductor device according to  claim 1 , wherein an impurity concentration of the second well and the third well is higher than an impurity concentration of the first well.  
   
   
       3 . The method for manufacturing a semiconductor device according to  claim 1 , wherein a low breakdown voltage transistor of the second conductivity type is formed at the second well, a low breakdown voltage transistor of the first conductivity type is formed at the third well, and a higher breakdown voltage transistor of the first conductivity type is formed at the first well.  
   
   
       4 . The method for manufacturing a semiconductor device according to  claim 1 , wherein a fourth well of the first conductivity type is formed in the semiconductor substrate.  
   
   
       5 . The method for manufacturing a semiconductor device according to  claim 4 , wherein a high breakdown voltage transistor of the second conductivity type is formed at the fourth well.  
   
   
       6 . The method for manufacturing a semiconductor device according to  claim 1 , wherein a ratio of the depths of the second well and the third well with respect to the first well is about 2 to 5, respectively.  
   
   
       7 . A method for manufacturing a semiconductor device, the method comprising: 
 (a) forming a first well in a semiconductor substrate;    (b) introducing impurities in specified regions of the first well to form a first impurity layer and a second impurity layer of opposite conductivity types; and    (c) diffusing the impurities in the first impurity layer and the second impurity layer to form a second well and a third well.    
   
   
       8 . The method for manufacturing a semiconductor device according to  claim 7 , wherein the second well and the third well are formed within the first well.  
   
   
       9 . The method for manufacturing a semiconductor device according to  claim 7 , wherein the first well and third well are a second conductivity type and the second well is a first conductivity type.  
   
   
       10 . The method for manufacturing a semiconductor device according to  claim 9 , wherein a fourth well of the first conductivity type is formed adjacent to the first well in the semiconductor substrate.  
   
   
       11 . The method for manufacturing a semiconductor device according to  claim 7 , wherein an impurity concentration of the second well and the third well is higher than an impurity concentration of the first well.  
   
   
       12 . The method for manufacturing a semiconductor device according to  claim 7 , wherein a low breakdown voltage transistor of the second conductivity type is formed at the second well, a low breakdown voltage transistor of the first conductivity type is formed at the third well, and a high breakdown voltage transistor of the first conductivity type is formed at the first well.  
   
   
       13 . The method for manufacturing a semiconductor device according to  claim 12 , wherein the high breakdown voltage transistor has an offset gate structure.  
   
   
       14 . The method for manufacturing a semiconductor device according to  claim 10 , wherein a high breakdown voltage transistor of the second conductivity type is formed at the fourth well.  
   
   
       15 . The method for manufacturing a semiconductor device according to  claim 14 , wherein the high breakdown voltage transistor has an offset gate structure.  
   
   
       16 . The method for manufacturing a semiconductor device according to  claim 7 , wherein a ratio of the depths of the second well and the third well with respect to the first well is about 2 to 5, respectively.  
   
   
       17 . The method according to  claim 7  wherein step (a) is different from and precedes steps (b) and (c).  
   
   
       18 . The method of  claim 7  wherein the depth of the first well is 10-20 μm and the depth of the second and third wells is 3-10 μm.  
   
   
       19 . The method of  claim 12  wherein the breakdown voltage of the low breakdown transistors is 1.8-5 volts and the breakdown voltage of the higher breakdown transistor is 20-60 volts.  
   
   
       20 . The method of  claim 13  which further comprises: 
 forming a gate electrode over a gate dielectric layer;    forming an offset impurity layer laterally adjacent the gate dielectric layer in the first well;    forming an element isolation layer to isolate the high breakdown transistor; and    forming channel stoppers under the element isolation layer.