US2005062133A1PendingUtilityA1

Structure and method for eliminating metal contact to P-well of N-well shorts or high leakage paths using polysilicon liner

Priority: Jan 15, 2003Filed: Oct 20, 2004Published: Mar 24, 2005
Est. expiryJan 15, 2023(expired)· nominal 20-yr term from priority
H10W 20/069H10B 12/485H10B 12/0383
42
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Claims

Abstract

A short or high leakage path from a metal contact to a P-well can occur when a contact via mask is misaligned with an active area mask, in combination with an overetch into the isolation oxide of an isolation trench which forms a divot in the isolation oxide, exposing the contact junction depletion region or even a P-well on the active area sidewall. This problem is prevented by using an N+ doped polysilicon liner, wherein an outdiffusion of N+ dopant from the poly liner forms an N+ halo extension in the active area silicon, providing a reverse biased junction between the metal contact stud and the P-well. The complementary structure and method of an N-well and P+ dopant are also disclosed

Claims

exact text as granted — not AI-modified
1 - 8 . (Cancelled).  
   
   
       9 . A semiconductor device which uses metal contact studs while preventing shorts from metal contacts to P-well active areas, wherein each contact via for each metal contact has an adjacent N+ outdiffusion region forming a reverse biased NP junction to the active area which is self aligning to an interface between the contact via and the active area to prevent a short or high leakage path between the contact via and the active area.  
   
   
       10 . The semiconductor device of  claim 9 , further including an N+ doped poly liner formed on sidewalls of each contact via.  
   
   
       11 - 18 . (Cancelled)  
   
   
       19 . A semiconductor device which uses metal contact studs while preventing shorts from metal contacts to N-well active areas, wherein each contact via for each metal contact has an adjacent P+ outdiffusion region forming a reverse biased PN junction to the active area which is self aligning to an interface between the contact via and the active area to prevent a short between the contact via and the active area.  
   
   
       20 . The semiconductor device of  claim 19 , further including a P+ doped poly liner formed on sidewalls of each contact via.

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