Method and system for molecular charge storage field effect transistor

Abstract

A method and/or system and/or apparatus for a molecular-based FET device (an m-FET) uses charge storing molecules ( 120 ) between a gate ( 110 ) and channel ( 105 ) of an FET-type transistor. Further embodiments describe fabrication methods for using combinations of standard practices in lithography and synthetic chemistry and novel elements.

1 . A charge storage transistor comprising: 
 a substrate comprising a channel region;    a source and a drain in electrical contact with said channel region, such that current can flow between said source and said drain through said channel region and affected by the conductance of said channel region;    one or more charge storage molecules proximate to said channel region, wherein charge stored on said molecules affects the conductance of said channel region; and    a gate proximate to said one or more charge storage molecules such that a voltage between said gate and said source or said drain will change the charge stored on said charge storage molecules.    
     
     
         2 . The transistor of  claim 1  further wherein: said one or more charge storage molecules comprise redox-active molecules, and said one or more charge storage molecules are attached to said channel region.  
     
     
         3 . The transistor of  claim 1  further wherein: 
 said one or more charge storage molecules are embedded in an electrolyte, and    said electrolyte is positioned above said channel region.    
     
     
         4 . The transistor of  claim 1  further wherein: 
 said one or more charge storage molecules are attached to one or more distal shielding groups, and    said distal shielding groups alter an electrolyte-molecule dipole capacitance of said one or more charge storage molecules.    
     
     
         5 . The transistor of  claim 1  further wherein: 
 said one or more charge storage molecules are attached to a linker; and    said linker is attached to said channel region.    
     
     
         6 . The transistor of  claim 1  further wherein: 
 said one or more charge storage molecules are embedded in an electrolyte,    said electrolyte is positioned above said channel region, and    a channel spacer is positioned between said charge storage molecules and said gate.    
     
     
         7 . The transistor of  claim 1  further wherein said transistor can be used as a memory element by placing charge on said one or more charge storage molecules using a voltage applied to said gate, said charge retained on said one or more charge storage molecules after voltage is removed from said gate.  
     
     
         8 . The transistor of  claim 7  further wherein charge on said one or more charge storage molecules can be detected by altering a source/drain current and detecting a resulting source/drain voltage.  
     
     
         9 . The transistor of  claim 7  further wherein charge on said one or more charge storage molecules can be detected by altering a source/drain voltage and detecting a resulting source/drain current.  
     
     
         10 . The transistor of  claim 7  further wherein said detecting comprises detecting a charge field imaged into said channel region from said one or more charge storage molecules without transferring any charge from said one or more charge storage molecules.  
     
     
         11 . The transistor of  claim 1  further wherein charge can be stored on said one or more charge storage molecules in a plurality of discrete charged states, said levels depending on voltage applied at said gate.  
     
     
         12 . The transistor of  claim 11  further wherein charge can be stored in said plurality of discrete charged states at room temperature.  
     
     
         13 . The transistor of  claim 11  further wherein charge can be stored in said plurality of discrete charged states using low voltages applied at said gate.  
     
     
         14 . The transistor of  claim 13  further wherein charge can be stored in said plurality of discrete charged states using gate/source or gate/drain voltages less than about 2 Volts.  
     
     
         15 . The transistor of  claim 13  further wherein charge can be stored in said plurality of discrete charged states using gate/source or gate/drain voltages less than about 3.3 Volts.  
     
     
         16 . The transistor of  claim 13  further wherein charge can be stored in said plurality of discrete charged states using gate/source or gate/drain voltages less than about 5.0 Volts.  
     
     
         17 . The transistor of  claim 11  further wherein said transistor can be used as a multi-bit memory element by placing charge on said one or more charge storage molecules in said plurality of discrete charged states, said charge retained at a quantized charge level on said one or more charge storage molecules after voltage is removed from said gate.  
     
     
         18 . The transistor of  claim 1  further wherein said one or more charge storage molecules exhibit robust and reproducible self-assembly on substrate surfaces such as silicon.  
     
     
         19 . The transistor of  claim 11  further wherein said transistor exhibits multilevel charge storage with inherent self-convergence, wherein because charge storage is discrete, there is no overwriting or overerasing.  
     
     
         20 . The transistor of  claim 6  further wherein: 
 charge can be stored on said one or more charge storage molecules in a plurality of discrete charged states;    said levels depending on voltage applied at said gate;    retention of charge is proportional to a linker length; and    said length can be tuned to provide a desired retention.    
     
     
         21 . The device according to  claim 20  wherein write and read times are inversely proportional to linker length.  
     
     
         22 . The device according to  claim 20  wherein optimization of read/write times can be attained by adjusting linker length.  
     
     
         23 . The transistor of  claim 6  further wherein said one or more charge storage molecules are attached to said channel region via a linker bearing a sulfur atom  
     
     
         24 . The transistor of  claim 6  further wherein said one or more charge storage molecules are attached to said channel region via a linker bearing an oxygen atom.  
     
     
         25 . The transistor of  claim 1  further wherein said one or more charge storage molecules are selected from the group consisting of porphyrinic macrocycle(s), metallocene(s), linear polyene(s), cyclic polyene(s), heteroatom-substituted linear polyene(s), heteroatom-substituted cyclic polyene(s), tetrathiafulvalene(s), tetraselenafulvalene(s), metal coordination complex(es), buckyball(s), triarylamine(s), 1,4-phenylenediamine(s), xanthene(s), flavin(s), phenazine(s), phenothiazine(s), acridine(s), quinoline(s), 2,2′-bipyridyl(s), 4,4′-bipyridyl(s), tetrathiotetracene(s), and peri-bridged naphthalene dichalcogenide(s).  
     
     
         26 . The transistor of  claim 1  further wherein said one or more charge storage molecules are selected from the group consisting of porphyrin(s), expanded porphyrin(s), contracted porphyrin(s), ferrocene(s), linear porphyrin polymer(s), porphyrinic sandwich complex(es), and porphyrin arrays.  
     
     
         27 . The transistor of  claim 1  further wherein said one or more charge storage molecules comprise one or more porphyrinic macrocycle(s) substituted at a β-position or at a meso- position.  
     
     
         28 . A method of fabricating a hybrid transistor comprising: 
 performing higher-temperature metal, semiconductor and insulator fabrication steps first; and    attaching one or more charge storage molecules at lower temperatures.    
     
     
         29 . The method according to  claim 28  further comprising: 
 using a temporary plug in a region that will contain said one or more charge storage molecules at lower temperatures;    completing higher-temperature fabrication; and    removing said temporary plug prior to said attaching.    
     
     
         30 . The method according to  claim 28  wherein said one or more charge storage molecules are porphyrin molecules.  
     
     
         31 . A method of fabricating a hybrid transistor comprising: 
 forming source/drain regions;    forming a gate region    first performing higher-temperature semiconductor and insulator fabrication steps; and    attaching one or more charge storage molecules at lower temperatures.    
     
     
         32 . The method according to  claim 31  further comprising: 
 growing a thick isolation oxide;    selectively etching said thick isolation oxide to form active areas;    using a dummy gate, made of polysilicon or other suitable material to form the dielectric region of the transistor;    depositing a layer of SiO 2 ;    polishing back said layer of SiO 2  using chemical and/or mechanical polishing;    removing said dummy gate using a selective wet etch;    performing an HF dip to remove any native oxide;    depositing charge storage molecules and an electrolyte;    depositing control gate metal;    removing metal/electrolyte from undesired regions; and    making contacts to the source and the drain.    
     
     
         33 . The method according to  claim 31  further comprising: 
 using a linker molecule for attaching said charge storage molecules to hydrogen-passivated Si.    
     
     
         34 . The method according to  claim 34  wherein said linker comprises one or more of: 
 alkyl, aryl, hydroxyalkyl, hydroxyaryl, mercaptoalkyl, mercaptoaryl, selenylalkyl, selenylaryl, tellurylalkyl, or tellurylaryl, cyanoalkyl, cyanoaryl, isocyanoalkyl, isocyanoaryl, carboxyalkyl, carboxyaryl, aminoalkyl, aminoaryl, dihydroxyphosphorylalkyl, dihydroxyphosphorylaryl, trichlorosilylalkyl, trichlorosilylaryl, trimethoxysilylalkyl, trimethoxysilylaryl linkers.    
     
     
         35 . The method according to  claim 31  further wherein: 
 a gel/electrolyte system is used to construct the dielectric region containing said charge storage molecules.    
     
     
         36 . The method according to  claim 35  further wherein: 
 material character and thickness of the gel/electrolyte system has a significant effect on the electrochemical characteristics of the memory storage element.    
     
     
         37 . The method according to  claim 35  further wherein the gel/electrolyte milieu affects one or more of: 
 homogeneity of the electrochemical response;    potential at which oxidation occurs; and    charge writing/reading speed.    
     
     
         38 . The method according to  claim 35  further wherein high-dielectric gels are used for solid-state operation.  
     
     
         39 . The method according to  claim 31  further wherein after the molecules and the electrolyte are in place, the gate electrode is deposited and defined using lithography.  
     
     
         40 . The method according to  claim 31  further wherein steps following the molecular placement are performed at low temperature so as not to disturb the integrity of said charge storage molecules.  
     
     
         41 . A method of forming a semiconductor structure, wherein the method comprises the steps of: 
 providing a semiconductor substrate;    forming a temporary feature having a first side and a second side over the semiconductor substrate;    forming spacers around said temporary feature over the semiconductor substrate;    forming a first doped region in the semiconductor substrate directly adjacent to the first side of the temporary feature and a second doped region in the semiconductor substrate directly adjacent to the second side of the temporary feature;    planarizing a top surface of the dielectric layer to expose a top portion of the temporary feature while leaving bottom-most regions of the dielectric layer on the surface of the semiconductor structure;    removing the temporary feature to form an opening in the dielectric layer;    filling the opening with a dielectric/charge storage molecule mixture to create a charge storage region; and    depositing a metal over said dielectric/charge storage molecule mixture to create a metal gate electrode.    
     
     
         42 . The method of  claim 41 , wherein the step of planarizing further comprises: 
 planarizing the top surface by polishing the top surface by using one of a chemical mechanical polishing process or an etch back process.    
     
     
         43 . The method of  claim 41 , wherein the step of removing the temporary feature further comprises: 
 removing the temporary feature by one of a wet etch process and a dry etch process.    
     
     
         44 . The method of  claim 41 , wherein the step of forming a temporary feature further comprises: 
 forming the temporary feature wherein the temporary feature includes one of a polysilicon and an amorphous silicon.    
     
     
         45 . The method of  claim 41 , wherein the step of forming a first doped region further comprises: 
 forming the first doped region and the second doped region by ion implantation in a self aligned manner.    
     
     
         46 . The method of  claim 41 , further comprising the step of: 
 forming a sidewall spacer on a vertical portion of the temporary feature.    
     
     
         47 . The method of  claim 41 , wherein the step of filling the opening further comprises: 
 placing one or more linker molecules in the opening to link to the surface of the channel region;    placing one or more charge storage molecules attached to said linker molecules;    placing a control-gate spacer between charge storage molecules and the control gate for said gate region to affect the dielectric properties of said charge storage molecules; and    filling the remainder of the opening with an electrolyte dielectric material.    
     
     
         48 . The method of  claim 41  wherein a gate dielectric region is formed after removing the feature.  
     
     
         49 . The method of  claim 41  wherein a channel region ion implantation is performed after removing the feature.  
     
     
         50 . The method of  claim 41 , wherein the step of forming a metallic gate includes forming the metallic electrode from material selected from a group consisting of: tungsten (W), titanium nitride (TiN), molybdenum (Mo), tungsten silicide (WSi 2 ), and nickel silicide (NiSi 2 ).  
     
     
         51 . The method of  claim 41  wherein sidewall spacers are formed within inner circumferences of the openings in the first and second dielectric layers.