Transparent software emulation as an alternative to hardware bus lock

Abstract

One of the disclosed embodiments comprises a method for software emulation of hardware bus lock in a computer system, comprising: acquiring a bus lock semaphore; providing the bus lock semaphore to a device attempting a bus lock operation; acquiring a page table semaphore; invalidating page table entries to prevent access to a location in the computer system referenced by the bus lock operation, wherein the location is an input/output (I/O) device; purging translation lookaside buffer pages associated with the location; and executing a clone instruction without lock semantics.

1 . An apparatus, implemented in a computer system, for emulating a hardware bus lock, the computer system comprising a central processing unit (CPU) executing an operating system (O/S), processors, and a main memory, the apparatus comprising: 
 the main memory accessible by the CPU and the processors, the main memory comprising a reserved memory block and a page table, wherein the reserved memory block stores a bus lock semaphore and a page table semaphore, and wherein page tables cross reference virtual addresses and physical addresses; and    a fault handler module operating on the CPU, the fault handler module including an emulation module wherein the fault handler receives and indication of an attempted operation capable of causing the hardware bus lock, wherein the operation comprises accessing a desired location in the computer system and an attempted simultaneous access to an input/output (I/O) device.    
   
   
       2 . The apparatus of  claim 1 , wherein the bus lock semaphore is invisible to the O/S.  
   
   
       3 . The apparatus of  claim 1 , wherein exclusive access to native page tables is maintained.  
   
   
       4 . The apparatus of  claim 1 , wherein the emulation module comprises: 
 means for purging page table entries in TLBs that correspond to invalidated page table entries;    means for defeating a fault-on-lock attempt behavior of a processor.    
   
   
       5 . The apparatus of  claim 2 , wherein the means for defeating the fault-on-lock attempt behavior is a mode bit set by the fault handler.  
   
   
       6 . The apparatus of  claim 3 , wherein the mode bit distinguishes between hardware bus lock and software emulation of hardware bus lock.  
   
   
       7 . A method, executed in a computer system including processors, translation lookaside buffers, translation lookaside buffers (TLBs) for translating between virtual addresses and physical addresses, and a memory, the memory including page tables for preventing a hardware bus lock by software emulation, the method comprising: 
 at a device in the computer system, attempting an operation capable of causing the hardware bus lock, wherein the operation comprises accessing a desired location in the computer system and attempted simultaneous access to an input/output (I/O) device;    at a fault handler, receiving an indication of the attempted operation and acquiring a bus lock semaphore;    caching the bus lock semaphore at a cache associated with the device;    at the fault handler: 
 invalidating selected page table entries, wherein access to the desired location is prevented, and  
 purging any TLB page tables associated with the desired location; and  
   executing an instruction sequence to cause a fault-on-the-bus-lock.    
   
   
       8  The method of  claim 7 , wherein executing the instruction sequence comprises re-executing the same instruction sequence as the attempted operation.  
   
   
       9 . The method of  claim 7 , wherein executing the instruction sequence comprises executing a clone routine that performs the same operation as the attempted operation without a lock semantic.  
   
   
       10 . The method of  claim 7 , wherein the device is a processor.  
   
   
       11 . The method of  claim 10 , wherein the processor accesses the main memory in a real mode, the method further comprising: 
 asserting an inter-processor interrupt; and    sending the interrupt to other processors in the computer system, the other processors entering a wait state in response to the interrupt, the other processors waking upon completion of the locked operation.    
   
   
       12 . A method for software emulation of hardware bus lock in a computer system, comprising: 
 acquiring a bus lock semaphore;    providing the bus lock semaphore to a device attempting a bus lock operation;    acquiring a page table semaphore;    invalidating page table entries to prevent access to a location in the computer system referenced by the bus lock operation, wherein the location is an input/output (I/O) device;    purging translation lookaside buffer pages associated with the location; and    executing a clone instruction without lock semantics.    
   
   
       13 . The method of  claim 12 , further comprising inserting local translation entries  
   
   
       14 . The method of  claim 12 , further comprising releasing the bus lock and page table semaphores.  
   
   
       15 . The method of  claim 12 , wherein the bus lock operation is attempted by a processor operating in a real mode, the method further comprising asserting an inter-processor interrupt.