Apparatus for sampling a plurality of analog signals

Abstract

An analog-to-digital conversion apparatus includes a sampling clock generator and an analog-to-digital converter. The sampling clock generator receives a clock signal and generates a plurality of sampling clock signals in response to phase control signals. The analog-to-digital converter receives a plurality of analog signals, samples the received analog signals and outputs digital signals synchronized with the sampling clock signals outputted from the sampling clock generator. The sampling clock signals outputted from the sampling clock generator correspond to the analog signals respectively. Therefore, the analog-to-digital converter can sample the inputted analog image signal when the inputted analog image signal is in the stable state. Thus, the analog-to-digital converter can output the optimal digital signal.

1 . A sampling apparatus comprising: 
 a clock generator for receiving a clock signal and generating sampling clock signals; and    a sampling circuit for receiving a plurality of analog signals and sampling the received analog signals synchronized with the sampling clock signals,    wherein the clock generator generates the sampling clock signals to change sampling points for the plurality of analog signals.    
   
   
       2 . The apparatus of  claim 1 , wherein each of the analog signals corresponds to each of the sampling clock signals in a one-to-one manner.  
   
   
       3 . The apparatus of  claim 2 , wherein the sampling circuit comprises a plurality of sampling units each corresponding to each of the plurality of analog signals, for sampling the corresponding analog signal synchronized with the corresponding sampling clock signal.  
   
   
       4 . The apparatus of  claim 2 , wherein the clock generator generates the sampling clock signals in response to phase control signals each corresponding to each of the analog signals.  
   
   
       5 . An analog-to-digital conversion apparatus comprising: 
 a clock generator for receiving a clock signal and generating sampling clock signals; and    an analog-to-digital converter for receiving a plurality of analog signals and converting the received analog signals into digital signals synchronized with the sampling clock signals,    wherein the clock generator generates the sampling clock signals for the analog-to-digital converter to change sampling points for the plurality of analog signals.    
   
   
       6 . The apparatus of  claim 5 , wherein the clock generator generates the sampling clock signals for the analog-to-digital converter to convert the analog signals into the digital signals when all the plurality of analog signals are in a stable state.  
   
   
       7 . The apparatus of  claim 5 , wherein the analog-to-digital converter comprises a plurality of conversion units each corresponding to each of the plurality of analog signals, for converting the corresponding analog signal into a digital signal synchronized with the corresponding sampling clock signal.  
   
   
       8 . The apparatus of  claim 7 , wherein the clock generator generates the sampling clock signals in response to phase control signals corresponding to the analog signals.  
   
   
       9 . The apparatus of  claim 8 , wherein the clock generator comprises clock delay circuits corresponding to the analog signals, for delaying the clock signal for a predetermined time and generating the sampling clock signal.  
   
   
       10 . The apparatus of  claim 8 , wherein each of the clock delay circuits delays the clock signal for a time corresponding to the received phase control signal and generates the sampling clock signal.  
   
   
       11 . The apparatus of  claim 10 , wherein each of the clock delay circuits comprises: 
 a plurality of delayers connected in series, for receiving the synchronization signal; and    a clock selector for outputting an output of a delayer corresponding to the received phase control signal among the delayers as a sampling clock signal.    
   
   
       12 . The apparatus of  claim 5 , wherein the clock generator comprises: 
 a plurality of delayers connected in series, for receiving the clock signal and outputting a clock signal delayed for a predetermined time; and    a plurality of delayed clock selectors corresponding to the plurality of analog signals, for outputting one of the delayed clock signals as the sampling clock signal in response to a received phase control signal.    
   
   
       13 . A flat panel display for receiving a synchronization signal and a plurality of analog image signals provided from a host and displaying an image, the device comprising: 
 a display panel;    analog-to-digital converters corresponding to the plurality of analog image signals, for converting the received analog image signals into digital signals in response to corresponding sampling clock signals and providing the display panel with the converted digital signals; and    a clock generator for receiving the synchronization signal and generating the sampling clock signals,    wherein the clock generator generates the sampling clock signals for the analog-to-digital converters to convert the received analog signal into a digital signal when each of the analog signals inputted to each of the analog-to-digital converters is in a stable state.    
   
   
       14 . The device of  claim 13 , wherein the clock generator comprises: a pixel clock generator for dividing a frequency of the synchronization signal and generating a pixel clock signal.  
   
   
       15 . The device of  claim 14 , wherein the clock generator comprises: clock delay circuits corresponding to the plurality of analog signals, for delaying the pixel clock signal for a predetermined time and generating a sampling clock signal.  
   
   
       16 . The device of  claim 14 , wherein the clock generator generates the sampling clock signals in response to phase control signals corresponding to the analog signals.  
   
   
       17 . The device of  claim 16 , wherein the clock delay circuit delays the synchronization signal for a predetermined time corresponding to a received phase control signal and generates a sampling clock signal.  
   
   
       18 . The device of  claim 17 , wherein the clock delay circuit comprises: 
 a plurality of delayers connected in series, for receiving the synchronization signal; and    a clock selector for outputting an output of a delayer corresponding to the received phase control signal among the delayers as the sampling clock signal.    
   
   
       19 . The device of  claim 15 , wherein the clock generator comprises: 
 a plurality of delayers connected in series, for receiving the clock signal and outputting a clock signal delayed for a predetermined time; and    a plurality of delayed clock selectors corresponding to the plurality of analog signals, for outputting one of the delayed clock signals as the sampling clock signal in response to a received phase control signal.    
   
   
       20 . The device of  claim 14 , wherein the clock generator further comprises: an output clock selector for supplying the display panel with one of the sampling clock signals outputted from the clock delay circuits as an output clock signal.  
   
   
       21 . The device of  claim 20 , wherein the display panel displays an N-channel digital signal outputted from the analog-to-digital converters synchronized with the output clock signal outputted from the clock generator.  
   
   
       22 . The device of  claim 13 , wherein the N-channel analog image signal comprises R (red)-, G (green)- and B (blue)-analog image signals.