Method of fabricating a semiconductor device

Abstract

This invention relates to Integrated Circuit (IC) processing and fabrication. A device and a method are provided for etching an opening in an insulating layer while depositing a barrier layer on the side walls of the opening without essentially depositing a barrier layer on the bottom of the opening.

1 . A device comprising an insulating layer on a substrate, the insulating layer having an opening, wherein side walls of the opening are covered with a barrier layer and a bottom of the opening is essentially not covered with the barrier layer, characterized in that the device is produced by a method comprising the steps of: 
 subjecting the substrate to a plasma, wherein the plasma is generated in a gaseous mixture comprising at least three components, the components comprising: a first component for depositing the metal barrier layer on at least the side walls of the opening, a second component for forming an opening in the insulating layer, and a third component for removing the barrier layer formed on the bottom of the opening; 
 etching the insulating layer with the plasma; and  
 depositing the barrier layer on the side walls of the opening with the plasma.  
   
     
     
         2 . A device as recited in  claim 1 , wherein the first component is selected from the group consisting of 1-methyl silane, 2-methyl silane, 3-methyl silane, 4-methyl-silane, a mixture of SiH 4  and N 2 , and mixtures thereof.  
     
     
         3 . A device as recited in  claim 1 , wherein the second component is selected from the group consisting of N x O y , C x F y H x O u , N 2 /O 2  mixtures, N 2 /H 2  mixtures, O 2 , O 3 , and mixtures thereof.  
     
     
         4 . A device as recited in  claim 1 , wherein the third component comprises a chemical compound that forms a halogen ion or a radical in the plasma.  
     
     
         5 . A device as recited in  claim 4 , wherein the third component is selected from the group consisting of NF 3 , SF 6 , F 2 , ClF 3 , and mixtures thereof.  
     
     
         6 . A device as recited in  claim 1 , wherein the gaseous mixture further comprises an inert gas.  
     
     
         7 . A device as recited in  claim 1 , wherein the plasma is a continuous plasma.  
     
     
         8 . A device as recited in  claim 1 , wherein the plasma is a pulsed plasma.  
     
     
         9 . A device as recited in  claim 1 , wherein the barrier layer is a metal diffusion barrier layer.  
     
     
         10 . A device as recited in  claim 9 , wherein the barrier layer comprises silicon carbide.  
     
     
         11 . A device as recited in  claim 1 , wherein the insulating layer comprises a porous material.  
     
     
         12 . A device as recited in  claim 1 , wherein the insulating is an organic containing insulating layer.  
     
     
         13 . A device as recited in  claim 1 , wherein the insulating layer is an inorganic containing insulating layer.  
     
     
         14 . A device as recited in  claim 1 , wherein the opening is a via hole, the via hole extending through the insulating layer to an underlying conductive layer or an underlying barrier layer.  
     
     
         15 . A device as recited in  claim 1 , the method for producing the device further comprising the steps of: 
 covering the insulating layer with a bilayer, the bilayer comprising a resist hard mask layer formed on the insulating layer and a resist layer formed on the hard mask layer; and    patterning the bilayer.