Improvements for on-die reflectance arrangements

Abstract

Improved semiconductor reflectance arrangements (e.g., semiconductor devices, systems including semiconductor devices, methods, etc.).

1 . A semiconductor device comprising: 
 a light reflective unit including at least one of: 
 a titanium interface layer disposed between a substrate and reflective layer portions;  
 an interface inter-layer dielectric (ILD) layer disposed between a planarized ILD and a reflective layer; and,  
 a post-plug-etch planarized ILD disposed between a substrate and a reflective layer.  
   
   
   
       2 . A semiconductor device as claimed in  claim 1 , comprising the light reflective unit including the titanium interface layer disposed between the substrate and reflective layer portions.  
   
   
       3 . A semiconductor device as claimed in  claim 2 , comprising a reflective enhancement coating (REC) of less than three stacked deposition layers on the reflective layer portions.  
   
   
       4 . A semiconductor device as claimed in  claim 2 , where the reflective layer portions include at least one of aluminum, copper, silver and gold material.  
   
   
       5 . A semiconductor device as claimed in  claim 1 , comprising the light reflective unit including the interface ILD layer disposed between the planarized ILD and the reflective layer.  
   
   
       6 . A semiconductor device as claimed in  claim 5 , where the interface ILD layer is one of a non-stressed, mono-stressed and substantially consistently stressed interface ILD layer.  
   
   
       7 . A semiconductor device as claimed in  claim 5 , where the interface ILD layer is one of a tetraethylorthosilicate (TEOS); plasma TEOS (PTEOS), thick TEOS, chemical vapor deposition (CVD) and a plasma enhanced CVD (PECVD) deposited interface ILD layer.  
   
   
       8 . A semiconductor device as claimed in  claim 5 , where the planarized ILD is one of a mechanically and a chemical mechanical polish (CMP) planarized ILD.  
   
   
       9 . A semiconductor device as claimed in  claim 1 , comprising the light reflective unit including the post-plug-etch planarized ILD disposed between the substrate and the reflective layer.  
   
   
       10 . A semiconductor device as claimed in  claim 9 , where the post-plug-etch planarized ILD is one of a mechanically and a chemical mechanical polish (CMP) post-plug-etch planarized ILD.  
   
   
       11 . A semiconductor device as claimed in  claim 9 , comprising at least one post-plug-etch planarized plug in the post-plug-etch planarized ILD, with major planarized surfaces of the at least one post-plug-etch planarized plug and the post-plug-etch planarized ILD being substantially co-planar with one another.  
   
   
       12 . A system comprising: 
 at least one item selected from a list of: an electronic package, PCB, socket, bus portion, input device, output device, power supply arrangement and case; and    a semiconductor device including: 
 a light reflective unit including at least one of: 
 a titanium interface layer disposed between a substrate and reflective layer portions;  
 an interface inter-layer dielectric (ILD) layer disposed between a planarized ILD and a reflective layer; and,  
 a post-plug-etch planarized ILD disposed between a substrate and a reflective layer.  
 
   
   
   
       13 . A system as claimed in  claim 12 , comprising the light reflective unit including the titanium interface layer disposed between the substrate and reflective layer portions.  
   
   
       14 . A system as claimed in  claim 13 , comprising a reflective enhancement coating (REC) of less than three stacked deposition layers on the reflective layer portions.  
   
   
       15 . A system as claimed in  claim 13 , where the reflective layer portions include at least one of aluminum, copper, silver and gold material.  
   
   
       16 . A system as claimed in  claim 12 , comprising the light reflective unit including the interface ILD layer disposed between the planarized ILD and the reflective layer.  
   
   
       17 . A system as claimed in  claim 16 , where the interface ILD layer is one of a non-stressed, mono-stressed and substantially consistently stressed interface ILD layer.  
   
   
       18 . A system as claimed in  claim 16 , where the interface ILD layer is one of a tetraethylorthosilicate (TEOS); plasma TEOS (PTEOS), thick TEOS, chemical vapor deposition (CVD) and a plasma, enhanced CVD (PECVD) deposited interface ILD layer.  
   
   
       19 . A system as claimed in  claim 16 , where the planarized ILD is one of a mechanically and a chemical mechanical polish (CMP) planarized ILD.  
   
   
       20 . A system as claimed in  claim 12 , comprising the light reflective unit including the post-plug-etch planarized ILD disposed between the substrate and the reflective layer.  
   
   
       21 . A system as claimed in  claim 20 , where the post-plug-etch planarized ILD is one of a mechanically and a chemical mechanical polish (CMP) post-plug-etch planarized ILD.  
   
   
       22 . A system as claimed in  claim 20 , comprising at least one post-plug-etch planarized plug in the post-plug-etch planarized ILD, with major planarized surfaces of the at least one post-plug-etch planarized plug and the post-plug-etch planarized ILD being substantially co-planar with one another.  
   
   
       23 . A method of forming a semiconductor device including a light reflective unit, the method comprising at least one of: 
 disposing a titanium interface layer between a substrate and reflective layer portions of the light reflective unit;    planarizing a base inter-layer dielectric (ILD) layer, and then depositing an interface ILD layer thereon before depositing a reflective layer of the light reflective unit; and,    applying planarization to a plug-etched ILD to obtain a post-plug-etch planarized ILD, before depositing a reflective layer of the light reflective unit.    
   
   
       24 . A method as claimed in  claim 23 , comprising the disposing of the titanium interface layer between the substrate and reflective layer portions of the light reflective unit.  
   
   
       25 . A method as claimed in  claim 24 , comprising depositing a reflective enhancement coating (REC) of less than three stacked deposition layers on the reflective layer portions.  
   
   
       26 . A method as claimed in  claim 24 , where the reflective layer portions include at least one of aluminum, copper, silver and gold material.  
   
   
       27 . A method as claimed in  claim 23 , comprising the planarizing of the base inter-layer dielectric (ILD) layer, and then depositing the interface ILD layer thereon before depositing the reflective layer of the light reflective unit.  
   
   
       28 . A method as claimed in  claim 27 , where the interface ILD layer is one of a non-stressed, mono-stressed and substantially consistently stressed interface ILD layer.  
   
   
       29 . A method as claimed in  claim 27 , where the interface ILD layer is deposited using at least one of a tetraethylorthosilicate (TEOS); plasma TEOS (PTEOS), thick TEOS, chemical vapor deposition (CVD) and a plasma enhanced CVD (PECVD) deposition.  
   
   
       30 . A method as claimed in  claim 27 , where the planarizing is performed using at least one of a mechanical and a chemical mechanical polish (CMP) planarization.  
   
   
       31 . A method as claimed in  claim 23 , comprising applying the planarization to the plug-etched ILD to obtain the post-plug-etch planarized ILD, before depositing the reflective layer of the light reflective unit.  
   
   
       32 . A method as claimed in  claim 31 , where the planarization is performed using at least one of a mechanical and a chemical mechanical polish (CMP) planarization.  
   
   
       33 . A method as claimed in  claim 31 , comprising planarizing to obtain at least one post-plug-etch planarized plug in the post-plug-etch planarized ILD, so as to have major planarized surfaces of the at least one post-plug-etch planarized plug and the post-plug-etch planarized ILD be substantially co-planar with one another.