Compiler instructions for vector transfer unit

Abstract

A compiler and vector data transfer instructions for use in a vector transfer unit for handling transfers of vector data between a memory and a data processor in a computer system. The compiler identifies the use of vector data in an application program and implements one or more vector instructions for transferring the vector data between memory and registers used to perform calculations on the vector data. A vector is partitioned by the compiler into variable-sized streams which are transferred into and out of the processor as burst transactions. The compiler schedules transfers of vector streams required in a calculation so that calculations on a portion of the vector data are performed while a subsequent portion of the vector data is transferred. A vector buffer pool is partitioned into one or more vector buffers and each vector buffer is used at a specific time. The compiler partitions a vector buffer into the variable-sized streams depending on the number of vectors buffers required by an application program and the size required for each stream. Each vector buffer is allocated for exclusive use by an application program that is executing in the data processor. A synchronization instruction is used to allow all VTU instructions issued prior to the synchronization instruction to finish before any VTU instructions issued after the synchronization instruction may begin. Instructions for controlling access to the vector buffer pool are also included.

1 - 30 . (Cancelled).  
   
   
       31 . A compiler for handling vector data in an application program, comprising: 
 a source code parser for identifying use of vector data in the application program;    an object code generator operable to implement at least one vector data instruction for transferring the vector data between a memory and a buffer when the source code parser identifies the use of vector data, the object code generator being further operable to implement a synchronization instruction to synchronize accessing the vector data with processing the vector data when the application program is executing.    
   
   
       32 . The compiler of  claim 31  wherein the at least one vector instruction transfers data from the memory to the buffer.  
   
   
       33 . The compiler of  claim 31  wherein the at least one vector instruction transfers data from the buffer to the memory.  
   
   
       34 . The compiler of  claim 31  wherein the at least one vector instruction transfers data from the buffer to a general purpose register.  
   
   
       35 . The compiler of  claim 31  wherein the at least one vector instruction transfers data from a general purpose register to the buffer.  
   
   
       36 . The compiler of  claim 31  wherein the at least one vector instruction is used to determine whether the buffer is available for use.  
   
   
       37 . The compiler of  claim 31  wherein the at least one vector instruction includes information about a vector stream including the starting address of the vector stream, and the length of the vector stream.  
   
   
       38 . The compiler of  claim 31  wherein the at least one vector instruction includes information about a vector stream including the stride of the vector stream, and the starting address of the buffer.  
   
   
       39 . The compiler of  claim 31  wherein the at least one vector instruction includes information about a vector stream including the width of the vector data in the data stream.  
   
   
       40 . The compiler of  claim 31  wherein the at least one vector instruction includes information about whether the vector data is integer or floating point data.  
   
   
       41 . A method comprising: 
 a compiler scheduling a transfer of a first stream of vector data between a processor and a memory; and    the compiler scheduling a transfer of a second stream of vector data between the processor and the memory so that the second stream of vector data is transferred while data of the first stream is processed.    
   
   
       42 . A computer-readable medium having stored thereon instructions which, when executed by a processor, configure the processor to: 
 schedule a first transfer of a first stream of vector data between the processor and a memory; and    schedule a second transfer of a second stream of vector data between the processor and the memory such that the second transfer occurs while data of the first stream of vector data is processed by the processor.    
   
   
       43 . The computer-readable medium of  claim 42  which further configures the processor to: 
 schedule the first transfer of the first stream of vector data between a vector buffer of the processor and the memory; and    schedule the second transfer of the second stream of vector data between the vector buffer and the memory such that the second transfer occurs while data of the first stream of vector data is processed by the processor.    
   
   
       44 . The computer-readable medium of  claim 43  wherein at least one of the first transfer and the second transfer is a burst transfer.  
   
   
       45 . The computer-readable medium of  claim 43  which further configures the processor to: 
 partition vector data of a computer program into a plurality streams.    
   
   
       46 . The computer-readable medium of  claim 42  which further configures the processor to: 
 detect vector data in a computer program.    
   
   
       47 . The computer-readable medium of  claim 46  which further configures the processor to: 
 detect a vector data indicator in the computer program, the vector data indicator identifying the vector data.    
   
   
       48 . The computer-readable medium of  claim 46  which further configures the processor to: 
 generate a vector instruction, wherein a stream of the plurality of streams is transferred from the memory to the vector buffer in response to execution of the vector instruction.    
   
   
       49 . The computer-readable medium of  claim 46  which further configures the processor to: 
 generate a vector instruction, wherein a stream of the plurality of streams is transferred from the vector buffer to the memory in response to the execution of the vector instruction.    
   
   
       50 . The computer-readable medium of  claim 46  which further configures the processor to: 
 generate a vector instruction, wherein a stream of the plurality of streams is transferred from the vector buffer to a register of the processor in response to the execution of the vector instruction.    
   
   
       51 . The computer-readable medium of  claim 46  which further configures the processor to: 
 generate a vector instruction, wherein a stream of the plurality of streams is transferred from a register of the processor to the vector buffer in response to the execution of the vector instruction.    
   
   
       52 . The computer-readable medium of  claim 42  which further configures the processor to: 
 generate a synchronization instruction to synchronize the first and second transfers while the data of the stream of vector data is processed by the processor.