US2005052802A1PendingUtilityA1

Complementary metal oxide semiconductor structure for battery protection circuit and battery protection circuit having the same

Priority: Oct 2, 2002Filed: Oct 15, 2004Published: Mar 10, 2005
Est. expiryOct 2, 2022(expired)· nominal 20-yr term from priority
Inventors:Chi-Chang Wang
H02J 7/80H02J 7/63H02J 7/62H02J 7/52H02J 7/61
37
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Claims

Abstract

A complementary metal-oxide semiconductor (CMOS) structure for a battery protection circuit and a battery protection circuit therewith. A tri-well technique or a buried layer technique is used for such CMOS structure to allow the battery protection circuit therewith to operate at different low voltage levels. Thereby, low voltage process can be realized to effectively reduce the cost of the chip and simplify the design.

Claims

exact text as granted — not AI-modified
1 - 8 . (canceled)  
   
   
       9 . A battery protection circuit to protect a battery pack, comprising: 
 a plurality of overcharging and over-discharging protection units, operative to monitor each voltage level for each battery of the battery pack;    an excess current protection unit, a short current protection unit and a voltage regulator, operative to monitor operation current of the battery pack to achieve current protection, wherein the voltage regulator provides voltage source to the excess current protection unit and the short current protection unit, such that unbalanced condition of the battery pack is avoided, wherein the overcharging and over-discharging, the excess current and short current protection units are formed by complementary metal oxide semiconductor using tri-well technique to form:    a level shift circuit, operative to connect the overcharging and over-discharging, the excess current protection unit and the short current protection unit and to adjust level of a plurality of comparison signals output from the protection units;    a logic and delay circuit, coupled to the level shift circuit to receive the adjusted comparison signals and output a Co signal and a Do signal according thereto, wherein when the level of the Co signal is logic 1, over-discharging or excess current and short current occurs, and when the level of the Do signal is logic 1, overcharging occurs.    
   
   
       10 . The battery protection circuit as claimed in  claim 9 , wherein the complementary metal oxide semiconductor structure of the overcharging and over-discharging and the excess current and short current protection units are formed by tri-well or buried layer technique.  
   
   
       11 . The battery protection unit as claimed in  claim 9 , wherein the complementary metal oxide semiconductor structure of the overcharging and over-discharging and excess current and short current protection units comprises: 
 a P-type substrate, having a P-well and an N-well adjacent to each other, wherein the P-well has an N-type buried layer isolated from the P-type substrate;    an N-type metal oxide semiconductor transistor formed in the P-well and a P-well formed in the N-well, wherein the N-type metal oxide semiconductor transistor has a gate coupled to an input terminal, a source coupled to a first voltage, and a drain coupled to an output terminal, the P-type metal oxide semiconductor transistor has a gate coupled to the input terminal, the source coupled to a second voltage, and a drain coupled to the output terminal, the first voltage is lower than the second voltage.    
   
   
       12 . The battery protection unit as claimed in  claim 9 , wherein the complementary metal oxide semiconductor structure of the overcharging and over-discharging and excess current and short current protection units comprises: 
 an N-type substrate, having a P-well and an N-well adjacent to each other, wherein the N-well further comprises a P-type buried layer isolated from the N-type substrate;    an N-type metal oxide semiconductor transistor formed in the P-well and a P-type metal oxide semiconductor transistor formed in the N-well, wherein the N-type metal oxide semiconductor transistor comprises a gate coupled to an input terminal, a source coupled to a first voltage level, a drain coupled to an output terminal, the P-type metal oxide semiconductor transistor comprises a gate coupled to the input terminal, a source coupled to a second voltage level, and a drain coupled to the output terminal, the first voltage level is lower than the second voltage level.    
   
   
       13 . The battery protection unit as claimed in  claim 9 , wherein the complementary metal oxide semiconductor structure of the overcharging and over-discharging and excess current and short current protection units comprises: 
 a P-type substrate, on which a deep N-well is formed, wherein the deep N-well comprises a P-well isolated from the P-type substrate;    an N-type metal oxide semiconductor formed in the P-well, having a gate coupled to an input terminal, a source coupled to a first voltage level, and a drain coupled to an output terminal; and    a P-type metal oxide semiconductor formed in the deep N-well, having a gate coupled to the input terminal, a source coupled to a second voltage level, and a drain coupled to the output terminal.    
   
   
       14 . The battery protection unit as claimed in  claim 9 , wherein the complementary metal oxide semiconductor structure of the overcharging and over-discharging and excess current and short current protection units comprises: 
 an N-type substrate, comprising a deep P-well and an N-well formed in the deep P-well isolated from the substrate;    an N-type metal oxide semiconductor transistor formed in the deep P-well, having a gate coupled to an input terminal, a source coupled to a first voltage level, and drain coupled to an output terminal; and    a P-type metal oxide semiconductor transistor formed in the N-well, having a gate coupled to an input terminal, a source coupled to a second voltage level, and drain coupled to an output terminal.    
   
   
       15 . The battery protection circuit as claimed in  claim 9 , wherein the overcharging and over-discharging protection circuit further comprises: 
 a first comparator and a second comparator; and    a bandgap reference voltage generating unit coupled to the first and second comparators; wherein    the first comparator is connected to one of a plurality of voltage levels to be monitored, and outputs the first signal after comparing a reference voltage provided by the bandgap reference voltage generating unit; and    the second comparator is connected to the voltage level monitored by the first comparator and outputs the second signal after comparing a reference provided by the bandgap reference voltage generating unit.    
   
   
       16 . The battery protection circuit as claimed in  claim 9 , wherein operation voltages of the overcharging and over-discharging protection units C 1 , C 2 , C 3  and C 4  are V1 to ground, V2 to V1, V3 to V2 and V4 to V3 each with a voltage difference of 5V to use a low voltage process.  
   
   
       17 . The battery protection circuit as claimed in  claim 9 , wherein the excess current and short current protection units are connected to the voltage input from a voltage detected by an external current sensor, the voltage input from the current sensor is generated by voltage variation of the highest voltage to ground in the voltage levels of the battery pack.  
   
   
       18 . The battery protection circuit as claimed in  claim 9 , wherein the voltage regulator comprises an operation amplifier and a high voltage transistor to generate an operation voltage equivalent to voltage V4 to V3 with a voltage difference of 5V, such that the excess current and the short current protection units are formed by a low voltage process.

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