Semiconductor device and method of manufacturing the same

Abstract

There is disclosed a semiconductor device having: a semiconductor substrate; a first gate electrode constructed of a multi-layered stack member provided in a memory region, formed with memory cells, of a surface area of the semiconductor substrate so that the first gate electrode is insulated by a first insulating layer from the semiconductor substrate; and a second gate electrode provided in a logic region, formed with a logic circuit for controlling at least the memory cells, of the surface area of the semiconductor substrate so that the second gate electrode is insulated by a second insulating layer from the semiconductor substrate, wherein said layer, brought into contact with the first insulating layer, of the first gate electrode and the layer, brought into contact with the second insulating layer, of the second gate electrode, are composed of materials different from each other. There is also disclosed a method of manufacturing a semiconductor device by defining a memory region for providing memory cells and a logic region for providing a logic circuit for controlling the memory cells, the memory and logic regions being isolated by a device isolation region on a semiconductor substrate; providing a first insulating layer on the semiconductor substrate; selectively removing said first insulating layer existing on the logic region in a surface area of the semiconductor substrate; stacking an amorphous silicon layer on the semiconductor substrate; and effecting a thermal treatment upon the semiconductor substrate in order to alter said amorphous silicon layer existing on said memory region into a polycrystalline semiconductor layer and to alter the amorphous silicon layer existing on the logic region into a silicon monocrystalline layer.

1 - 14 . (Canceled)  
   
   
       15 . A method of manufacturing a semiconductor device comprising: 
 defining a memory region for providing memory cells and a logical region for providing a logical circuit for controlling said memory cells, said memory and logic regions being isolated by a device isolation region on a semiconductor substrate;    providing a first insulating layer on said semiconductor substrate;    selectively removing said first insulating layer existing on said logic region in a surface area of said semiconductor substrate;    stacking an amorphous silicon layer on said semiconductor substrate; and    effecting a thermal treatment upon said semiconductor substrate in order to alter said amorphous silicon layer existing on said memory region into a polycrystalline semiconductor layer and to alter said amorphous silicon layer existing on said logic region into a silicon monocrystalline layer.    
   
   
       16 . A method of manufacturing a semiconductor device according to  claim 15 , further comprising: 
 providing a second insulating layer and a third insulating layer respectively on said silicon monocrystalline layer and on said polycrystalline silicon layer in the same process;    stacking a first polycrystalline silicon germanium layer and a second polycrystalline silicon germanium layer respectively on said second insulating layer and said third insulating layer in the same process;    selectively etching said second polycrystalline silicon germanium layer, said third insulating layer and said polycrystalline silicon layer to provide a first gate electrode in said memory region; and    selectively etching said first polycrystalline silicon germanium layer and said second insulating layer in said logic region.    
   
   
       17 . A method of manufacturing a semiconductor device according to  claim 16 , wherein impurities are, after providing said second gate electrode, implanted in a direction inclined at an angle α from a direction perpendicular to the surface of said semiconductor substrate, the angle α meeting the following relationship:  
       tan −1 ( s′/h′ )≦α≦tan −1 ( s/h )  
     where s is a minimum distance of a distance between said first gate electrodes adjacent to each other, h is a height from the bottom surface of said second insulating layer up to an upper surface of said gate electrode, s′ is a minimum distance of a distance between said second gate electrodes adjacent to each other, and h′ is a height from the surface of said semiconductor substrate up to the upper surface of said gate electrode.  
   
   
       18 . A method of manufacturing a semiconductor device according to  claim 17 , wherein said angle α is set such as 30°≦α≦60°.  
   
   
       19 . A method of manufacturing a semiconductor device according to  claim 17 , wherein silicide layers are provided on said second and first polycrystalline silicon germanium layers subjected to patterning in said memory region and said logic region after executing said implanting step.  
   
   
       20 . A method of manufacturing a semiconductor device according to  claim 19 , wherein ions are implanted for providing high-concentration impurity diffused layers serving as a source and a drain before providing said silicide layers.  
   
   
       21 . A method of manufacturing a semiconductor device according to  claim 15 , wherein the channel impurities are implanted comparatively shallow into the surface area of said semiconductor substrate in said logical region before stacking said amorphous silicon layer.