Memory module and method having on-board data search capabilities and processor-based system using such memory modules

Abstract

A memory module includes several memory devices coupled to a memory hub. The memory hub includes several link interfaces coupled to respective processors, several memory interfaces coupled to respective memory devices, and a cross-bar switch coupling any of the link interfaces to any of the memory interfaces. Each memory interface includes a memory controller, a write buffer, a read cache, and a data mining module. The data mining module includes a search data memory that is coupled to the link interface to receive and store at least one item of search data. A comparator receives both the read data from the memory device and the search data. The comparator then compares the read data to the respective item of search data and provides a hit indication in the event of a match.

1 . A memory hub for use with a memory device, the memory hub comprising: 
 a link interface for receiving memory requests;    a memory device interface coupled to the link interface, the memory device interface outputting write memory requests and write data, the memory device interface further outputting read memory requests and receiving read data in response thereto; and    a data mining module coupled to the link interface, the data mining module being operable to receive at least one item of search data through the link interface, to repetitively cause read memory requests to be output from the memory hub, to receive read data responsive to each of the read memory requests, and to compare the received read data to the at least one item of search data.    
   
   
       2 . The memory hub of  claim 1 , further comprising a plurality of link interfaces, a plurality of memory device interfaces, and a switch for selectively coupling one of the plurality of link interfaces and one of the plurality of memory device interfaces.  
   
   
       3 . The memory hub of  claim 1  wherein the data mining module is operable to generate the read memory requests and to output the read memory requests from the memory hub.  
   
   
       4 . The memory hub of  claim 1  wherein the data mining module comprises: 
 a direct memory access engine coupled to the link interface, the direct memory access engine being operable to generate the read memory requests;    a search data memory coupled to the link interface to receive and store the at least one item of search data; and    a comparator for each item of search data stored in the search data memory, each comparator being coupled to receive a respective item of search data from the search data memory and being coupled to receive the read data, the comparator being operable to compare the read data to the respective item of search data and provide a hit indication in the event of a match.    
   
   
       5 . The memory hub of  claim 4  wherein an output of the comparator is coupled to the link interface to couple the hit indication to the link interface.  
   
   
       6 . The memory hub of  claim 4  wherein the data mining module further comprises a memory device sequencer coupled to the direct memory access engine, the memory device sequencer generating a set of command and address signals for each of the read requests.  
   
   
       7 . The memory hub of  claim 4  wherein the search data memory stores a plurality of the search data items, and wherein the data mining module comprises a plurality of comparators corresponding in number to the number of search data items stored in the search data memory.  
   
   
       8 . The memory hub of  claim 4  further comprising a results memory coupled to an output of the comparator to store each of the hit indications generated by each of the comparators.  
   
   
       9 . The memory hub of  claim 8  wherein the results memory is operable to store a memory device address corresponding to the read data that resulted in each of the hit indications.  
   
   
       10 . The memory hub of  claim 9  wherein the results memory is further operable to store with each of the memory device addresses a corresponding item of search data.  
   
   
       11 . The memory hub of  claim 1  wherein the link interface, the memory device interface, and the data mining module are fabricated as an integrated circuit on a common semiconductor substrate.  
   
   
       12 . A memory module, comprising: 
 a plurality of memory devices; and    a memory hub, comprising: 
 a link interface for receiving memory requests for access to at least one of the memory devices;  
 a memory device interface coupled to the link interface and to the memory devices, the memory device interface coupling write memory requests and write data to the memory devices, the memory device interface further coupling read memory requests to the memory devices and coupling read data from the memory devices; and  
 a data mining module coupled to at least one of the memory devices, the data mining module being operable to receive at least one item of search data through the link interface, to repetitively cause read memory requests to be output from the memory hub, to receive read data responsive to each of the read memory requests, and to compare the received read data to the at least one item of search data.  
   
   
   
       13 . The memory module of  claim 12  wherein the data mining module is operable to generate the read memory requests and to output the read memory requests from the memory hub.  
   
   
       14 . The memory module of  claim 12  wherein the memory hub further comprises a plurality of link interfaces, a plurality of memory device interfaces coupled to a respective memory device, and a switch for selectively coupling one of the plurality of link interfaces and one of the plurality of memory device interfaces.  
   
   
       15 . The memory module of  claim 14  wherein one of the data mining modules is provided for each of the memory device interfaces, each of the data mining modules being coupled to the memory device to which the respective memory device interface is coupled.  
   
   
       16 . The memory module of  claim 14  wherein the memory module includes a single data mining module that is coupled to each of the memory device interfaces through the switch.  
   
   
       17 . The memory module of  claim 12  wherein the data mining module comprises: 
 a direct memory access engine coupled to the link interface, the direct memory access engine being operable to generate the read memory requests for coupling to the memory devices;    a search data memory coupled to the link interface to receive and store the at least one item of search data; and    a comparator for each item of search data stored in the search data memory, each comparator being coupled to receive a respective item of search data from the search data memory and being coupled to receive the read data from the memory devices, the comparator being operable to compare the read data to the respective item of search data and provide a hit indication in the event of a match.    
   
   
       18 . The memory module of  claim 17  wherein an output of the comparator is coupled to the link interface to couple the hit indication to the link interface.  
   
   
       19 . The memory module of  claim 17  wherein the data mining module further comprises a memory device sequencer coupled to the direct memory access engine and to the memory devices, the memory device sequencer generating a set of command and address signals for coupling to the memory devices for each of the read requests.  
   
   
       20 . The memory module of  claim 17  wherein the search data memory stores a plurality of the search data items, and wherein the data mining module comprises a plurality of comparators corresponding in number to the number of search data items stored in the search data memory.  
   
   
       21 . The memory module of  claim 17  further comprising a results memory coupled to an output of the comparator to store each of the hit indications generated by each of the comparators.  
   
   
       22 . The memory module of  claim 21  wherein the results memory is operable to store a memory device address indicative of a location in the memory devices where read data that resulted in each of the hit indications was stored.  
   
   
       23 . The memory module of  claim 22  wherein the results memory is further operable to store with each of the memory device addresses a corresponding item of search data that matched read stored at the respective address.  
   
   
       24 . The memory module of  claim 12  wherein the plurality of memory devices comprises a plurality of synchronous random access memory devices.  
   
   
       25 . The memory module of  claim 12  wherein the link interface, the memory device interface, and the data mining module are fabricated as an integrated circuit on a common semiconductor substrate.  
   
   
       26 . The memory module of  claim 26  wherein the common semiconductor substrate further comprises the memory devices.  
   
   
       27 . A memory module, comprising: 
 a memory device; and    a memory hub, comprising: 
 a link interface for receiving memory requests for access to the memory device;  
 a memory device interface coupled to the link interface and to the memory device, the memory device interface coupling write memory requests and write data to the memory device, the memory device interface further coupling read memory requests to the memory device and coupling read data from the memory device;  
 a direct memory access engine coupled to the link interface, the direct memory access engine being operable to generate the read memory requests for coupling to the memory device;  
 a search data memory coupled to the link interface to receive and store the at least one item of search data; and  
 a comparator for each item of search data stored in the search data memory, each comparator being coupled to receive a respective item of search data from the search data memory and being coupled to receive the read data from the memory device, the comparator being operable to compare the read data to the respective item of search data and provide a hit indication in the event of a match.  
   
   
   
       28 . The memory module of  claim 27  wherein the memory module comprises a plurality of memory devices, and wherein the memory hub further comprises a plurality of link interfaces, a plurality of memory device interfaces coupled to a respective memory device, and a switch for selectively coupling one of the plurality of link interfaces and one of the plurality of memory device interfaces.  
   
   
       29 . The memory module of  claim 27  wherein an output of the comparator is coupled to the link interface to couple the hit indication to the link interface.  
   
   
       30 . The memory module of  claim 27  wherein the data mining module further comprises a memory device sequencer coupled to the direct memory access engine and to the memory devices, the memory device sequencer generating a set of command and address signals for each of the read requests for coupling to the memory device.  
   
   
       31 . The memory module of  claim 27  wherein the search data memory stores a plurality of the search data items, and wherein the memory hub comprises a plurality of comparators corresponding in number to the number of search data items stored in the search data memory.  
   
   
       32 . The memory module of  claim 27  further comprising a results memory coupled to an output of the comparator to store each of the hit indications generated by each of the comparators.  
   
   
       33 . The memory module of  claim 27  wherein the results memory is operable to store a memory device address indicative of a location in the memory devices where read data that resulted in each of the hit indications was stored.  
   
   
       34 . The memory module of  claim 33  wherein the results memory is further operable to store with each of the memory device addresses a corresponding item of search data that matched read stored at the respective address.  
   
   
       35 . The memory module of  claim 27  wherein the plurality of memory devices comprises a plurality of synchronous random access memory devices.  
   
   
       36 . The memory module of  claim 27  wherein the link interface, the memory device interface, the direct memory access engine, the search data memory, and the comparator for each item of search data stored in the search data memory are fabricated as an integrated circuit on a common semiconductor substrate.  
   
   
       37 . The memory module of  claim 36  wherein the common semiconductor substrate further comprises the memory device.  
   
   
       38 . A processor-based system, comprising: 
 a processor having a processor bus;    a system controller coupled to the processor bus, the system controller having a system memory port and a peripheral device port;    at least one input device coupled to the peripheral device port of the system controller;    at least one output device coupled to the peripheral device port of the system controller;    at least one data storage device coupled to the peripheral device port of the system controller; and    a memory module coupled to the system memory port of the system controller, the memory module comprising: 
 a plurality of memory devices; and  
 a memory hub, comprising: 
 a link interface for receiving memory requests for access to at least one of the memory devices;  
 a memory device interface coupled to the link interface and to the memory devices, the memory device interface coupling write memory requests and write data to the memory devices, the memory device interface further coupling read memory requests to the memory devices and coupling read data from the memory devices; and  
 a data mining module coupled to at least one of the memory devices, the data mining module being operable to receive at least one item of search data through the link interface, to repetitively cause read memory requests to be output from the memory hub, to receive read data responsive to each of the read memory requests, and to compare the received read data to the at least one item of search data.  
 
   
   
   
       39 . The processor-based system of  claim 38  wherein the data mining module is operable to generate the read memory requests and to output the read memory requests from the memory hub.  
   
   
       40 . The processor-based system of  claim 38  wherein the memory hub further comprises a plurality of link interfaces, a plurality of memory device interfaces coupled to a respective memory device, and a switch for selectively coupling one of the plurality of link interfaces and one of the plurality of memory device interfaces.  
   
   
       41 . The processor-based system of  claim 40  wherein one of the data mining modules is provided for each of the memory device interfaces, each of the data mining modules being coupled to the memory device to which the respective memory device interface is coupled.  
   
   
       42 . The processor-based system of  claim 40  wherein the memory module includes a single data mining module that is coupled to each of the memory devices through the switch.  
   
   
       43 . The processor-based system of  claim 38  wherein the data mining module comprises: 
 a direct memory access engine coupled to the link interface, the direct memory access engine being operable to generate the read memory requests for coupling to the memory devices;    a search data memory coupled to the link interface to receive and store the at least one item of search data; and    a comparator for each item of search data stored in the search data memory, each comparator being coupled to receive a respective item of search data from the search data memory and being coupled to receive the read data from the memory devices, the comparator being operable to compare the read data to the respective item of search data and provide a hit indication in the event of a match.    
   
   
       44 . The processor-based system of  claim 43  wherein an output of the comparator is coupled to the link interface to couple the hit indication to the link interface.  
   
   
       45 . The processor-based system of  claim 43  wherein the data mining module further comprises a memory device sequencer coupled to the direct memory access engine and to the memory devices, the memory device sequencer generating a set of command and address signals for coupling to the memory devices for each of the read requests.  
   
   
       46 . The processor-based system of  claim 43  wherein the search data memory stores a plurality of the search data items, and wherein the data mining module comprises a plurality of comparators corresponding in number to the number of search data items stored in the search data memory.  
   
   
       47 . The processor-based system of  claim 43  further comprising a results memory coupled to an output of the comparator to store each of the hit indications generated by each of the comparators.  
   
   
       48 . The processor-based system of  claim 47  wherein the results memory is operable to store a memory device address indicative of a location in the memory devices where read data that resulted in each of the hit indications was stored.  
   
   
       49 . The processor-based system of  claim 48  wherein the results memory is further operable to store with each of the memory device addresses a corresponding item of search data that matched read stored at the respective address.  
   
   
       50 . The processor-based system of  claim 38  wherein the plurality of memory devices comprises a plurality of synchronous random access memory devices.  
   
   
       51 . The processor-based system of  claim 38  wherein the link interface, the memory device interface, and the data mining module are fabricated as an integrated circuit on a common semiconductor substrate.  
   
   
       52 . The processor-based system of  claim 51  wherein the common semiconductor substrate further comprises the memory devices.  
   
   
       53 . A processor-based system, comprising: 
 a processor having a processor bus;    a system controller coupled to the processor bus, the system controller having a system memory port and a peripheral device port;    at least one input device coupled to the peripheral device port of the system controller;    at least one output device coupled to the peripheral device port of the system controller;    at least one data storage device coupled to the peripheral device port of the system controller; and    a memory module coupled to the system memory port of the system controller, the memory module comprising: 
 a memory device; and  
 a memory hub, comprising:  
 a link interface for receiving memory requests for access to the memory device;  
 a memory device interface coupled to the link interface and to the memory device, the memory device interface coupling write memory requests and write data to the memory device, the memory device interface further coupling read memory requests to the memory device and coupling read data from the memory device;  
 a direct memory access engine coupled to the link interface, the direct memory access engine being operable to generate the read memory requests for coupling to the memory device;  
 a search data memory coupled to the link interface to receive and store the at least one item of search data; and  
 a comparator for each item of search data stored in the search data memory, each comparator being coupled to receive a respective item of search data from the search data memory and being coupled to receive the read data from the memory device, the comparator being operable to compare the read data to the respective item of search data and provide a hit indication in the event of a match.  
   
   
   
       54 . The processor-based system of  claim 53  wherein the memory module comprises a plurality of memory devices, and wherein the memory hub further comprises a plurality of link interfaces, a plurality of memory device interfaces coupled to a respective memory device, and a switch for selectively coupling one of the plurality of link interfaces and one of the plurality of memory device interfaces.  
   
   
       55 . The processor-based system of  claim 53  wherein an output of the comparator is coupled to the link interface to couple the hit indication to the link interface.  
   
   
       56 . The processor-based system of  claim 53  wherein the data mining module further comprises a memory device sequencer coupled to the direct memory access engine and to the memory devices, the memory device sequencer generating a set of command and address signals for each of the read requests for coupling to the memory device.  
   
   
       57 . The processor-based system of  claim 53  wherein the search data memory stores a plurality of the search data items, and wherein the memory hub comprises a plurality of comparators corresponding in number to the number of search data items stored in the search data memory.  
   
   
       58 . The processor-based system of  claim 53  further comprising a results memory coupled to an output of the comparator to store each of the hit indications generated by each of the comparators.  
   
   
       59 . The processor-based system of  claim 58  wherein the results memory is operable to store a memory device address indicative of a location in the memory devices where read data that resulted in each of the hit indications was stored.  
   
   
       60 . The processor-based system of  claim 59  wherein the results memory is further operable to store with each of the memory device addresses a corresponding item of search data that matched read stored at the respective address.  
   
   
       61 . The processor-based system of  claim 53  wherein the plurality of memory devices comprises a plurality of synchronous random access memory devices.  
   
   
       62 . The processor-based system of  claim 53  wherein the link interface, the memory device interface, the direct memory access engine, the search data memory, and the comparator for each item of search data stored in the search data memory are fabricated as an integrated circuit on a common semiconductor substrate.  
   
   
       63 . The processor-based system of  claim 62  wherein the common semiconductor substrate further comprises the memory device.  
   
   
       64 . A method of searching for items of search data stored in a memory device that is located in a memory module, the method comprising: 
 passing at least one item of search data to the memory module;    storing the at least one item of search data from within the memory module;    sequentially initiating a plurality of read memory requests in the memory module;    sequentially coupling the read memory requests to the memory device;    receiving read data at the memory module responsive to each of the read memory requests;    comparing the received read data to the at least one item of search data within the memory module to determine if there is a data match;    generating a results indication responsive to each data match; and    coupling the results indication from the memory module.    
   
   
       65 . The method of  claim 64  wherein the act of generating a results indication responsive to each data match comprises providing a memory device address indicative of a location in the memory devices where read data that resulted in each of the data matches was stored.  
   
   
       66 . The method of  claim 65  wherein the act of generating a results indication responsive to each data match further comprises providing with each memory device address a corresponding item of search data that was matched.  
   
   
       67 . The method of  claim 64 , further comprising storing the results indication responsive to each data match prior to coupling the results indication from the memory module.  
   
   
       68 . In a processor-based system having a processor coupled to a system controller having a system memory port, a method of searching for items of search data stored in a system memory device that is located in a memory module, the method comprising: 
 coupling at least one item of search data from the processor to the memory module;    storing the at least one item of search data in the memory module;    sequentially initiating a plurality of read memory requests from within the memory module;    coupling the read memory requests to the memory device;    coupling read data from the memory device responsive to each of the read memory requests;    comparing the read data to the at least one item of search data within the memory module to determine if there is a data match;    generating a results indication responsive to each data match; and    coupling the results indication from the memory module to the processor.    
   
   
       69 . The method of  claim 68  wherein the act of generating a results indication responsive to each data match comprises providing a memory device address indicative of a location in the memory devices where read data that resulted in each of the data matches was stored.  
   
   
       70 . The method of  claim 69  wherein the act of generating a results indication responsive to each data match further comprises providing with each memory device address a corresponding item of search data that was matched.  
   
   
       71 . The method of  claim 68 , further comprising storing the results indication within the memory module responsive to each data match prior to coupling the results indication from the memory module to the processor.  
   
   
       72 . The method of  claim 68  wherein the act of coupling the read memory requests to the memory device and the act of coupling the read data from the memory device are performed entirely within the memory module.