Apparatus and method for high density multi-chip structures

Abstract

Devices and methods are described including a multi-chip assembly. Embodiments of multi-chip assemblies are provided that uses both lateral connection structures and through chip connection structures. One advantage of this design includes an increased number of possible connections. Another advantage of this design includes shorter distances for interconnection pathways, which improves device performance and speed.

1 . A multi-chip assembly, comprising: 
 a number of chips, including: 
 at least one memory chip;  
 at least one logic chip;  
   a number of chip edge connection structures adapted to couple selected chips in the number of chips; and    a number of through chip connection structures adapted to couple selected chips in the number of chips.    
   
   
       2 . The multi-chip assembly of  claim 1 , wherein the number of chips are formed substantially into a cube assembly.  
   
   
       3 . The multi-chip assembly of  claim 2 , wherein at least one logic chip is attached to an external side of the cube assembly.  
   
   
       4 . The multi-chip assembly of  claim 1 , further including a polymer insulation layer between at least two chips in the number of chips.  
   
   
       5 . The multi-chip assembly of  claim 4 , wherein the polymer insulation layer includes a polyimide insulation layer.  
   
   
       6 . The multi-chip assembly of  claim 4 , wherein the polymer insulation layer includes cells of a gaseous component within the layer.  
   
   
       7 . The multi-chip assembly of  claim 4 , wherein the polymer insulation layer is a hydrophilic polymer.  
   
   
       8 . The multi-chip assembly of  claim 1 , further including a number of corner connections that connect at least two chips that are oriented at an angle to each other.  
   
   
       9 . A multi-chip assembly, comprising: 
 a number of chips, including: 
 at least one memory chip;  
 at least one logic chip;  
   a number of chip edge connection structures adapted to couple selected chips in the number of chips; and    a number of through chip coaxial connections adapted to couple selected chips in the number of chips.    
   
   
       10 . The multi-chip assembly of  claim 9 , wherein the number of chips are formed substantially into a cube assembly.  
   
   
       11 . The multi-chip assembly of  claim 10 , wherein at least one logic chip is attached to an external side of the cube assembly.  
   
   
       12 . The multi-chip assembly of  claim 9 , further including a foamed polymer insulation layer between at least two chips in the number of chips.  
   
   
       13 . The multi-chip assembly of  claim 12 , wherein the foamed polymer insulation layer includes a polynorbornene insulation layer.  
   
   
       14 . The multi-chip assembly of  claim 12 , further including a hydrophilic layer attached to the foamed polymer insulation layer.  
   
   
       15 . A multi-chip assembly, comprising: 
 a number of chips, including: 
 at least one memory chip;  
 at least one logic chip;  
   a number of chip edge connection structures adapted to couple selected chips in the number of chips; and    a number of through chip optical waveguide connections adapted to couple selected chips in the number of chips.    
   
   
       16 . The multi-chip assembly of  claim 15 , wherein the number of chips are formed substantially into a cube assembly.  
   
   
       17 . The multi-chip assembly of  claim 16 , wherein at least one logic chip is attached to an external side of the cube assembly.  
   
   
       18 . The multi-chip assembly of  claim 15 , further including a foamed polymer insulation layer between at least two chips in the number of chips.  
   
   
       19 . The multi-chip assembly of  claim 18 , wherein the foamed polymer insulation layer includes a hydrophilic polymer.  
   
   
       20 . The multi-chip assembly of  claim 18 , further including a hydrophilic layer attached to the foamed polymer insulation layer.  
   
   
       21 . The multi-chip assembly of  claim 20 , wherein the hydrophilic layer includes methane radicals.  
   
   
       22 . An information handling system, comprising: 
 a display;    an input controller;    a multi-chip assembly, including 
 a number of chips, including: 
 at least one memory chip;  
 at least one logic chip;  
 
 a number of chip edge connection structures adapted to couple selected chips in the number of chips;  
 a number of through chip connection structures adapted to couple selected chips in the number of chips; and  
   a bus connecting the display, the input controller, and the multi-chip assembly.    
   
   
       23 . The information handling system of  claim 22 , wherein the number of chips are formed substantially into a cube assembly.  
   
   
       24 . The information handling system of  claim 23 , wherein at least one logic chip is attached to an external side of the cube assembly.  
   
   
       25 . The information handling system of  claim 24 , wherein at least one logic chip includes a processor chip.  
   
   
       26 . A method of forming a multi-chip assembly, comprising: 
 forming a number of chip edge connection structures in selected chips of a number of chips;    forming a number of through chip connection structures in selected chips of the number of chips; and    interconnecting portions of the number of chips using the chip edge connection structures and the through chip connection structures, wherein at least one logic chip and at least one memory chip are included in the number of chips.    
   
   
       27 . The method of  claim 26 , wherein forming a number of chip edge connection structures and forming a number of through chip connection structures includes forming at least one chip edge connection structure and at least one through chip connection structure on each chip in the number of chips.  
   
   
       28 . The method of  claim 26 , wherein forming a number of through chip connection structures includes forming a number of coaxial conductor structures.  
   
   
       29 . The method of  claim 26 , wherein forming a number of through chip connection structures includes forming a number of optical waveguide structures.  
   
   
       30 . The method of  claim 26 , further including forming an insulator layer between two adjacent chips in the number of chips.  
   
   
       31 . The method of  claim 30 , wherein forming an insulator layer includes forming a polymer insulator layer that includes a number of cells of gaseous components.  
   
   
       32 . The method of  claim 26 , wherein interconnecting portions of the number of chips includes forming the number of chips in a cube structure.  
   
   
       33 . The method of  claim 32 , wherein interconnecting portions of the number of chips in the cube structure includes interconnecting a number of memory chips with at least one logic chip on an outside face of the cube structure.  
   
   
       34 . A method of forming a multi-chip assembly, comprising: 
 forming a number of chip edge connection structures in selected chips of a number of chips;    forming a number of through chip connection structures in selected chips of the number of chips;    reducing the thickness of at least one chip in the number of chips; and    interconnecting portions of the number of chips using the chip edge connection structures and the through chip connection structures, wherein at least one logic chip and at least one memory chip are included in the number of chips.    
   
   
       35 . The method of  claim 34 , further including forming an insulator layer between two adjacent chips in the number of chips.  
   
   
       36 . The method of  claim 35 , further including forming a hydrophilic layer coupled to an exterior surface of the insulator layer.  
   
   
       37 . The method of  claim 35 , wherein forming an insulator layer includes forming a polymer insulator layer that includes a number of cells of gaseous components.  
   
   
       38 . The method of  claim 37 , wherein forming a polymer insulator layer that includes a number of cells of gaseous components includes utilizing a supercritical fluid to form the number of cells of gaseous components.  
   
   
       39 . The method of  claim 34 , wherein interconnecting portions of the number of chips includes forming the number of chips in a cube structure.  
   
   
       40 . The method of  claim 39 , wherein interconnecting portions of the number of chips in the cube structure includes interconnecting a number of memory chips with at least one logic chip on an outside face of the cube structure.  
   
   
       41 . A method of forming a multi-chip assembly, comprising: 
 forming a number of chip edge connection structures in selected chips of a number of chips;    forming a number of through chip connection structures in selected chips of the number of chips;    forming an insulator layer between two adjacent chips in the number of chips, the insulating layer including cells of a gaseous component; and    interconnecting portions of the number of chips using the chip edge connection structures and the through chip connection structures, wherein at least one logic chip and at least one memory chip are included in the number of chips.    
   
   
       42 . The method of  claim 41 , further including forming a hydrophilic layer coupled to an exterior surface of the insulator layer.  
   
   
       43 . The method of  claim 42 , wherein forming a hydrophilic layer coupled to an exterior surface of the insulator layer includes coupling methane radicals to an exterior surface of the insulator layer.  
   
   
       44 . The method of  claim 41 , further including reducing the thickness of at least one chip in the number of chips.  
   
   
       45 . The method of  claim 41 , wherein forming an insulator layer between two adjacent chips includes utilizing a supercritical fluid to form the cells of a gaseous component.  
   
   
       46 . The method of  claim 45 , wherein utilizing a supercritical fluid to form the cells of a gaseous component includes utilizing supercritical carbon dioxide to form the cells of a gaseous component.  
   
   
       47 . A multi-chip assembly, comprising: 
 a number of chips, including: 
 at least one memory chip;  
 at least one logic chip;  
   means for coupling edges of selected chips in the number of chips; and    means for coupling through a thickness of selected chips in the number of chips.    
   
   
       48 . The multi-chip assembly of  claim 47 , wherein the means for coupling edges of selected chips in the number of chips includes metal traces.  
   
   
       49 . The multi-chip assembly of  claim 47 , wherein the means for coupling through a thickness of selected chips in the number of chips includes coaxial conductors.  
   
   
       50 . The multi-chip assembly of  claim 47 , wherein the means for coupling through a thickness of selected chips in the number of chips includes optical waveguides.