Wafer-level chip scale package

Abstract

A chip scale package implements solder bars to form a connection between a chip and a trace, formed in a substrate, such as another chip or PCB. Solder bars are formed by depositing one or more solder layers into the socket, or optionally, depositing a base metal layer into the socket and applying the solder layer to the base metal layer. The geometry of a solder bars may be rectangular, square, or other regular or irregular geometry. Solder bars provide a greater utilization of the connectivity footprint and increase the electrical and thermal flow capacity. Solder bars also provide a robust connection.

1 . A method of constructing a preformed solder bar made-ready for installing a microchip, comprising: 
 forming a socket on a first surface of a microchip, such that the socket has predetermined physical dimensions complementary to those of a microchip connection pad footprint occupied by at least one contact pad area on the microchip,    the socket presenting a conductive base capable of bonding to solder;    bonding solder to the conductive base to place a solder bar in the socket and place the microchip in made-ready condition for installation.    
     
     
         2 . The method of  claim 1 , wherein the microchip contains a silicon wafer and the step of forming the socket comprises 
 depositing an adhesion layer onto the wafer, and    depositing under-bump-metallization (UBM) material contacting the adhesion layer to complete formation of the conductive base.    
     
     
         3 . The method of  claim 2 , wherein the step of depositing the adhesion layer includes depositing a conductor selected from the group consisting of aluminum, nickel-vanadium, titanium, tungsten and copper.  
     
     
         4 . The method of  claim 2 , wherein the step of depositing the UMB material includes depositing a conductor selected from at least one of titanium, tungsten, vanadium, tin, copper, aluminum, gold, silver, and lead.  
     
     
         5 . The method of  claim 1 , wherein the step of forming the socket includes the predetermined dimensions selected from the group consisting of rectangular, “E,” “L,” and “U” shapes.  
     
     
         6 . The method of  claim 1 , wherein the step of forming the socket includes the physical dimensions selected from the group consisting of ring, square, and circular shapes.  
     
     
         7 . The method of  claim 1 , wherein the step of forming the socket includes the physical dimensions being complimentary to the solder bar having a planar rectilinear configuration.  
     
     
         8 . The method of  claim 1 , wherein the step of forming the socket includes the physical dimensions being complimentary to the solder bar having a planar curvilinear configuration.  
     
     
         9 . The method of  claim 1 , wherein the step of forming the socket further comprising a step of forming a passivation layer on substantially all of the first surface, exclusive of an area where the socket is located.  
     
     
         10 . The method of  claim 9 , wherein the step of forming the passivation layer includes the steps of: 
 applying one or more layers of passivation material to the entire first surface; and    removing selected portions of the passivation material covering the area where the socket is to be located.    
     
     
         11 . The method of  claim 10 , wherein the step of applying one or more layers of passivation material includes applying at least one layer selected from the group consisting of polysilicon, silicon dioxide, and benzocyclobutane.  
     
     
         12 . The method of  claim 1 , further comprises depositing a non-solder base metal in the socket after the step of forming the socket and prior to the step of bonding solder, such that the solder bar contains the non-solder base metal and the solder in respective layers.  
     
     
         13 . The method of  claim 12 , wherein the step of depositing the non-solder base metal includes electroplating the non-solder base metal.  
     
     
         14 . A method of  claim 12 , wherein the step of depositing the non-solder base metal includes screen printing at least one base metal layer.  
     
     
         15 . The method of  claim 14 , wherein the step of depositing the non-solder base metal includes depositing the non-solder base metal layer selected from the group consisting of copper, gold, titanium, tungsten, and vanadium.  
     
     
         16 . The method of  claim 1 , wherein the step of bonding solder includes electroplating one or more solder layers onto the conductive base.  
     
     
         17 . The method of  claim 1 , wherein the step of bonding solder includes screen printing one or more solder layers onto the conductive base.  
     
     
         18 . A chip scale package made-ready for installation of a microchip on a printed circuit board or chip-on-chip stack, comprising: 
 a microchip including a first surface having a connection pad area;    an adhesion layer contacting the connection pad;    an under bump metallization layer contacting the adhesion layer;    at least one passivation layer delineating an opening to the under bump metallization layer to define a socket; and    a solder bar in contact with the under bump metallization layer, the solder bar having dimensions complementary to the socket and a geometric configuration selected from the group consisting of planar curvilinear and planar rectilinear configurations.    
     
     
         19 . The chip scale package of  claim 18 , wherein the solder bar includes a base metal layer in contact with the under bump metallization layer and the solder layer.  
     
     
         20 . The chip scale package of  claim 18 , wherein the geometric configuration includes a geometry selected from the group consisting of rectangular, “E,” “L,” and “U” shapes.  
     
     
         21 . The chip scale package of  claim 18 , wherein the geometric configuration includes a geometry selected from the group consisting of ring, square, and circular shapes.  
     
     
         22 . The chip scale package of  claim 18 , wherein the solder bar comprises a plurality of sublayers having different characteristics.  
     
     
         23 . The chip scale package of  claim 18 , wherein the solder bar contains a base metal layer and a solder layer  24 . The chip scale package of  claim 23 , wherein the base metal layer is selected form the group consisting of copper, gold, silver, lead, tin, titanium, tungsten, and vanadium.