US2005045590A1PendingUtilityA1

FRAM capacitor stack clean

Priority: May 28, 2003Filed: Sep 10, 2004Published: Mar 3, 2005
Est. expiryMay 28, 2023(expired)· nominal 20-yr term from priority
H10P 70/18H10P 50/285H10P 50/267H10D 1/682G03F 7/428G03F 7/427Y10S134/902G03F 7/423G03F 7/42
44
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Claims

Abstract

An embodiment of the invention is a method of cleaning a material stack 2 that has a hard mask top layer 8 . The method involves cleaning the material stack 2 with a fluorine-based plasma etch. The method further involves rinsing the material stack 2 with a wet clean process.

Claims

exact text as granted — not AI-modified
1 - 16 . (Cancelled)  
     
     
         17 . A method of manufacturing a semiconductor wafer having a ferroelectric capacitor stack having a hard mask top layer comprising: 
 forming a layer of bottom electrode material;    forming a layer of dielectric material over said layer of bottom electrode material;    forming a layer of top electrode material over said layer of dielectric material;    forming a layer of hard mask material over said layer of top electrode material;    forming a layer of photoresist over said layer of hard mask material;    patterning said photoresist;    etching said photoresist;    etching said hard mask material;    ashing said photoresist;    etching said layer of top electrode material, said layer of dielectric material, and said layer of bottom electrode material to form said ferroelectric capacitor stack;    cleaning said ferroelectric capacitor stack with a fluorine-based plasma etchant; and    rinsing said ferroelectric capacitor stack with a wet clean process.    
     
     
         18 . The method of  claim 17  wherein said fluorine-based plasma etchant is CF 4 /O 2 .  
     
     
         19 . The method of  claim 17  wherein said fluorine-based plasma etchant is NF 3 .  
     
     
         20 . The method of  claim 17  wherein said fluorine-based plasma etchant is C 2 F 6 .  
     
     
         21 . The method of  claim 17  wherein said wet clean process is a deionized water rinse.  
     
     
         22 . The method of  claim 17  wherein said wet clean process is a deionized water rinse followed by a hydrochloric acid rinse.  
     
     
         23 . The method of  claim 17  wherein said wet clean process is a deionized water rinse followed by a phosphoric acid rinse.  
     
     
         24 . The method of  claim 17  wherein said wet clean process is a deionized water rinse followed by an organic solvent rinse.  
     
     
         25 . The method of  claim 17  wherein said wet clean process is an organic solvent rinse.  
     
     
         26 . The method of  claim 17  wherein said wet clean process is a phosphoric acid rinse.  
     
     
         27 . The method of  claim 17  wherein said wet clean process is a dilute HCl acid rinse.  
     
     
         28 . The method of  claim 17  wherein said rinsing step further etches said ferroelectric capacitor stack.  
     
     
         29 . The method of  claim 17  wherein said rinsing step further includes the use of ultrasonic energy.  
     
     
         30 . The method of  claim 17  wherein said layer of hard mask material comprises a bottom layer of TiAlN, a middle layer of TiAlON, and a top layer of TiAlN.  
     
     
         31 . The method of  claim 17  wherein said layer of dielectric material is PZT.  
     
     
         32 . A method of manufacturing a semiconductor wafer having a ferroelectric capacitor stack comprising: 
 sputter depositing a first layer of iridium;    metal organic chemical vapor depositing a layer of PZT over said first layer of iridium;    physical vapor depositing a second layer of iridium over said layer of PZT;    reactive physical vapor depositing a layer of iridium oxide over said second layer of iridium;    sputter depositing a first layer of TiAlN over said layer of iridium oxide;    sputter depositing a layer of TiAlON over said first layer TiAlN;    sputter depositing a second layer of TiAlN over said layer of TiAlON;    forming a layer of photoresist over said second layer of TiAlN;    patterning said photoresist;    etching said photoresist;    etching said second layer of TiAlN said layer of TiAlON, and said first layer of TiAlN;    ashing said photoresist;    etching said layer of iridium oxide, said second layer of iridium, said layer of PZT, and said first layer of iridium to form said ferroelectric capacitor stack;    cleaning said ferroelectric capacitor stack with a CF 4 /O 2  plasma etchant;    rinsing said ferroelectric capacitor stack with deionized water; and    rinsing said ferroelectric capacitor stack with dilute hydrochloric acid.

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