Method for eliminating reaction between photoresist and OSG

Abstract

A method of forming a microelectronic device while preventing photoresist poisoning. Various layers of conductive metals and dielectric materials are deposited onto a substrate in selective sequence to form an integrated circuit. Vias and trenches are formed throughout the structure by exposing and patterning a photoresist material. The dielectric materials of the insulating layers are protected from the photoresist to prevent chemical reactions which lead to photoresist poisoning. This is done by forming a modified surface layer on the dielectric material by either depositing an additional layer that covers the dielectric material, or by modifying the exposed surface of the dielectric material to a plasma or chemical treatment.

1 . (Canceled)  
     
     
         2 . The process of  claim 18  wherein the first dielectric layer comprises an organic dielectric material and the second dielectric layer comprises an inorganic dielectric material.  
     
     
         3 . The process of  claim 18  wherein the first dielectric layer comprises an inorganic dielectric material and the second dielectric layer comprises an organic dielectric material.  
     
     
         4 . The process of  claim 18  wherein the first dielectric layer comprises an inorganic dielectric material and the second dielectric layer comprises an inorganic dielectric material.  
     
     
         5 . The process of  claim 18  wherein the first dielectric layer comprises an organic dielectric material and the second dielectric layer comprises an organic dielectric material.  
     
     
         6 . The process of  claim 18  wherein the etch stop layer is present.  
     
     
         7 . The process of  claim 6  wherein the etch stop layer comprises silicon nitride, silicon oxynitride, silicon dioxide, silicon carbide, silicon oxycarbide, spin on glass, organic polymers, hydrogen silsesquioxane, methyl silsesquioxane or combinations thereof.  
     
     
         8 . The process of  claim 18  wherein the optional etch stop layer is not present and wherein the first dielectric layer and the second dielectric layer have significantly different etch resistance properties.  
     
     
         9 . The process of  claim 18  wherein the optional etch stop layer is not present and wherein the first dielectric layer and the second dielectric layer have substantially the same etch resistance properties.  
     
     
         10 . (Canceled)  
     
     
         11 . The process of  claim 18  wherein the barrier metal comprises Ti, Ta, or a nitride.  
     
     
         12 . The process of  claim 18  wherein the fill metal comprises aluminum, aluminum alloys, copper, copper alloys, tantalum, tungsten, titanium, nitrides thereof or combinations thereof.  
     
     
         13 - 17 . (Canceled).  
     
     
         18 . A process for producing a microelectronic device which comprises: 
 (a) forming a first dielectric layer on a substrate;    (b) forming an optional etch stop layer on the first dielectric layer;    (c) forming a second dielectric layer on the first dielectric layer or the optional etch stop layer; )    (d) depositing a layer of a photoresist on a top surface of the second dielectric layer and imagewise removing a portion of the photoresist corresponding to at least one via for the first dielectric layer;    (e) removing the portions of each layer which are under the removed portions of the photoresist thus forming at least one via through the second dielectric layer, optional etch stop and first dielectric layer, and removing the balance of the photoresist layer;    (f) depositing a barrier material on a top surface of the second dielectric layer, and a surface of inside walls and a floor of the via through the second dielectric layer, optional etch stop and first dielectric layer thus forming a barrier material layer thereon;    (g) depositing an additional layer of a photoresist on the barrier material layer on the top surface of the second dielectric layer and on the walls and a floor of the via through the second dielectric layer, optional etch stop layer, and first dielectric layer, and imagewise removing a portion of the photoresist corresponding to at least one trench for the second dielectric layer;    (h) removing the portions of the barrier material layer on the top surface of the second dielectric layer, the second dielectric layer, and the barrier material layers on the walls of the via within the second dielectric layer which are under the removed portion of the additional photoresist layer thus forming at least one trench down through the second dielectric layer, and removing the balance of the additional photoresist layer;    (i) lining a barrier metal on inside walls and a floor of the trench, and on the inside walls and floor of the via; and    (j) filling the trench and via with a fill metal in contact with the barrier metal lining.    
     
     
         19 . The process of  claim 18  wherein the barrier layer material comprises CVD oxide, CVD nitride, CVD oxynitride, CVD SiC, spin on glass, organic polymers, chromophore laden spin on glass, hydrogen silsesquioxane, methyl silsesquioxane, metals and combinations thereof.  
     
     
         20 . A process for producing a microelectronic device which comprises: 
 (a) forming a first dielectric layer on a substrate;    (b) forming an optional etch stop layer on the first dielectric layer;    (c) forming a second dielectric layer on the first dielectric layer or the optional etch stop layer;    (d) depositing a layer of a photoresist on a top surface of the second dielectric layer and imagewise removing a portion of the photoresist corresponding to at least one via for the second dielectric layer and the optional etch stop layer;    (e) removing the portions of the second dielectric layer and the optional etch stop layer which are under the removed portions of the photoresist thus forming at least one via down through the second dielectric layer and the optional etch stop layer, and removing the balance of the photoresist layer;    (f) depositing a barrier material on a top surface of the second dielectric layer, and a surface of inside walls and a floor of the via through the second dielectric layer and optional etch stop layer thus forming a barrier material layer thereon;    (g) depositing an additional layer of a photoresist on the barrier material layer on the top surface of the second dielectric layer and on the walls and a floor of the via through the second dielectric layer and the optional etch stop layer, and imagewise removing a portion of the photoresist corresponding to at least one trench for the second dielectric layer;    (h) removing the portions of the barrier material layer on the top surface of the second dielectric layer, the second dielectric layer, and the barrier material layers on the walls of the via within the second dielectric layer which are under the removed portion of the additional photoresist layer thus forming at least one trench down through the second dielectric layer, and removing the portions of the barrier material layer from the floor of the via which was in the second dielectric layer, and portions of the first dielectric layer under the via which was in the second dielectric layer thus forming at least one via down through the first dielectric layer;    (i) removing the balance of the additional photoresist layer;    (j) lining a barrier metal on inside walls and a floor of the trench, and on the inside walls and floor of the via; and    (k) filling the trench and via with a fill metal in contact with the barrier metal lining.    
     
     
         21 . A process for producing a microelectronic device which comprises: 
 (a) forming a first dielectric layer on a substrate;    (b) forming an optional etch stop layer on the first dielectric layer;    (c) forming a second dielectric layer on the first dielectric layer or the optional etch stop layer;    (d) depositing a layer of a photoresist on a top surface of the second dielectric layer and imagewise removing a portion of the photoresist corresponding to at least one trench for the second dielectric layer;    (e) removing the portions of the second dielectric layer which are under the removed portions of the photoresist thus forming at least one trench through the second dielectric layer, and removing the balance of the photoresist layer;    (f) modifying a top surface of the second dielectric layer, and a surface of inside walls and a floor of the trench thus forming a protective material thereon;    (g) depositing an additional layer of a photoresist on the protective material on the top surface of the second dielectric layer, and the protective material on the walls and floor of the trench, and imagewise removing a portion of the photoresist corresponding to at least one via for the first dielectric layer;    (h) removing the portions of each layer which are under the removed portion of the additional photoresist layer thus forming at least one via down through the first dielectric layer, and removing the balance of the additional photoresist layer;    (i) lining a barrier metal on inside walls and a floor of the trench, and on inside walls and a floor of the via; and    (j) filling the trench and via with a fill metal in contact with the barrier metal lining.    
     
     
         22 . A process for producing a microelectronic device which comprises: 
 (a) forming a first dielectric layer on a substrate;    (b) forming an optional etch stop layer on the first dielectric layer;    (c) forming a second dielectric layer on the first dielectric layer or the optional etch stop layer;    (d) depositing a layer of a photoresist on a top surface of the second dielectric layer and imagewise removing a portion of the photoresist corresponding to at least one trench for the second dielectric layer;    (e) removing the portions of the second dielectric layer and optionally removing the etch stop layer, if present, which are under the removed portions of the photoresist thus forming at least one trench through the second dielectric layer and optionally through the etch stop layer, and removing the balance of the photoresist layer;    (f) depositing a barrier material on a top surface of the second dielectric layer, and a surface of inside walls and a floor of the trench thus forming a barrier material layer thereon;    (g) depositing an additional layer of a photoresist on the barrier material layer on the top surface of the second dielectric layer and the inside walls and floor of the trench, and imagewise removing a portion of the photoresist corresponding to at least one via for the first dielectric layer;    (h) removing the portions of each of the barrier material layer on the floor of the trench, any remaining portions of the etch stop layer, and portions of the first dielectric layer which are under the removed portion of the additional photoresist layer, thus forming at least one via down through the barrier material layer on the floor of the trench, the optional etch stop layer, and the first dielectric layer, and removing the balance of the additional photoresist layer;    (i) lining a barrier metal on the barrier material layer on the inside walls and floor of the trench, and on inside walls and a floor of the via; and    (j) filling the trench and via with a fill metal in contact with the barrier metal lining.    
     
     
         23 . A process for producing a microelectronic device which comprises: 
 (a) forming a first dielectric layer on a substrate;    (b) forming an optional etch stop layer on the first dielectric layer;    (c) forming a second dielectric layer on the first dielectric layer or the optional etch stop layer;    (d) forming a first hardmask layer on the second dielectric layer;    (e) forming a second hardmask layer on the first hardmask layer;    (f) depositing a layer of a photoresist on a top surface of the second hardmask layer and imagewise removing a portion of the photoresist corresponding to at least one via for the second hardmask layer;    (g) removing the portions of the second hardmask layer which are under the removed portions of the photoresist thus forming at least one via through the second hardmask layer, and removing the balance of the photoresist layer;    (h) depositing an additional layer of a photoresist on the top surface of the second hardmask layer and on inside walls and floor of the via in the second hardmask, and imagewise removing a portion of the photoresist corresponding to at least one trench for the second hardmask layer;    (i) removing the portions of the first hardmask layer and the second dielectric layer which are under the via in the second hardmask layer thus forming at least one via down through the first hardmask layer and the second dielectric layer;    (j) removing the portions of the second hardmask layer which are under the removed portions of the additional photoresist thus forming at least one trench down through the second hardmask layer, and removing the portions of the optional etch stop layer which are under the via in the second dielectric layer thus extending the via down through the optional etch stop layer;    (k) removing the portions of the first hardmask layer and the second dielectric layer which are under the trench in the second hardmask layer thus forming at least one trench down through the first hardmask layer and the second dielectric layer; removing the portions of the first dielectric layer under the via which was in the second dielectric layer thus forming a via through the first dielectric layer, and removing the balance of the additional photoresist layer;    (l) lining a barrier metal on inside walls and a floor of the trench, and on inside walls and a floor of the via; and    (m) filling the trench and via with a fill metal in contact with the barrier metal lining.    
     
     
         24 . The process of  claim 23  wherein the first hardmask layer and the second hardmask layer comprise dissimilar materials selected from the group consisting of SiO 2 , Si 3 N 4 , SiOC, SiC, SiN, SiON, spin on glass, chromophore laden spin on glass, organic spin on polymers, hydrogen silsesquioxane, methyl silsesquioxane, metals and combinations thereof.  
     
     
         25 . A process for producing a microelectronic device which comprises: 
 (a) forming a first dielectric layer on a substrate;    (b) forming an optional etch stop layer on the first dielectric layer;    (c) forming an second dielectric layer on the first dielectric layer or the optional etch stop layer;    (d) forming a first hardmask layer on the second dielectric layer;    (e) forming a second hardmask layer on the first hardmask layer;    (f) depositing a layer of a photoresist on a top surface of the second hardmask layer and imagewise removing a portion of the photoresist corresponding to at least one trench for the second hardmask layer;    (g) removing the portions of the second hardmask layer which are under the removed portions of the photoresist thus forming at least one trench through the second hardmask layer, and removing the balance of the photoresist layer;    (h) depositing an additional layer of a photoresist on the top surface of the second hardmask layer and on inside walls and floor of the trench, and imagewise removing a portion of the photoresist corresponding to at least one via for the second dielectric layer and the optional etch stop layer;    (i) removing the portions of the first hardmask layer, the second dielectric layer, and the optional etchstop layer which are under the removed portion of the additional photoresist layer thus forming at least one via down through the second dielectric layer and optional etch stop layer, and removing the balance of the additional photoresist layer;    (j) removing the portions of the first hardmask layer and the second dielectric layer which are under the trench in the second hardmask layer thus forming at least one trench down through the second dielectric layer and removing the portions of the first dielectric layer corresponding to the via in the second dielectric layer or optional etch stop layer, thus forming at least one via down through the first dielectric layer;    (k) lining a barrier metal on inside walls and a floor of the trench, and on inside walls and a floor of the via; and    (l) filling the trench and via with a fill metal in contact with the barrier metal lining.    
     
     
         26 . The process of  claim 25  wherein the first hardmask layer and the second hardmask layer comprise dissimilar materials selected from the group consisting of SiO 2 , Si 3 N 4 , SiOC, SiC, SiN, SiON, spin on glass, chromophore laden spin on glass, organic spin on polymers, hydrogen silsesquioxane, methyl silsesquioxane, metals and combinations thereof.  
     
     
         27 . The process of  claim 20  wherein the etch stop layer is present.  
     
     
         28 . The process of  claim 20  wherein the optional etch stop layer is not present and wherein the first dielectric layer and the second dielectric layer have significantly different etch resistance properties.  
     
     
         29 . The process of  claim 21  wherein the etch stop layer is present.  
     
     
         30 . The process of  claim 21  wherein the optional etch stop layer is not present and wherein the first dielectric layer and the second dielectric layer have significantly different etch resistance properties.  
     
     
         31 . The process of  claim 22  wherein the etch stop layer is present.  
     
     
         32 . The process of  claim 22  wherein the optional etch stop layer is not present and wherein the first dielectric layer and the second dielectric layer have significantly different etch resistance properties.  
     
     
         33 . The process of  claim 23  wherein the etch stop layer is present.  
     
     
         34 . The process of  claim 23  wherein the optional etch stop layer is not present and wherein the first dielectric layer and the second dielectric layer have significantly different etch resistance properties.  
     
     
         35 . The process of  claim 25  wherein the etch stop layer is present.  
     
     
         36 . The process of  claim 25  wherein the optional etch stop layer is not present and wherein the first dielectric layer and the second dielectric layer have significantly different etch resistance properties.