Semiconductor processing methods of forming integrated circuitry

Abstract

Semiconductor processing methods of forming integrated circuitry are described. In one embodiment, memory circuitry and peripheral circuitry are formed over a substrate. The peripheral circuitry comprises first and second type MOS transistors. Second type halo implants are conducted into the first type MOS transistors in less than all of the peripheral MOS transistors of the first type. In another embodiment, a plurality of n-type transistor devices are formed over a substrate and comprise memory array circuitry and peripheral circuitry. At least some of the individual peripheral circuitry n-type transistor devices are partially masked, and a halo implant is conducted for unmasked portions of the partially masked peripheral circuitry n-type transistor devices. In yet another embodiment, at least a portion of only one of the source and drain regions is masked, and at least a portion of the other of the source and drains regions is exposed for at least some of the peripheral circuitry n-type transistor devices. A halo implant is conducted relative to the exposed portions of the source and drain regions. In another embodiment, a common masking step is used and a halo implant is conducted of devices formed over a substrate comprising memory circuitry and peripheral circuitry sufficient to impart to at least three of the devices three different respective threshold voltages.

1 - 4 . (Cancelled).  
   
   
       5 . A semiconductor processing method comprising: 
 a masking step providing a common mask; and    an implant step carried out through the common mask, comprising conducting a halo implant of devices formed over a substrate comprising memory circuitry and peripheral circuitry sufficient to impart to at least three of the devices three different respective threshold voltages.    
   
   
       6 . The method of  claim 5 , wherein said three devices comprise peripheral circuitry.  
   
   
       7 . The method of  claim 5 , wherein said three devices comprise NMOS field effect transistors.  
   
   
       8 . The method of  claim 5 , wherein said three devices comprise NMOS field effect transistors comprising peripheral circuitry.  
   
   
       9 . The method of  claim 5 , wherein said three devices comprise PMOS field effect transistors.  
   
   
       10 . The method of  claim 5 , wherein said three devices comprise PMOS field effect transistors comprising peripheral circuitry.  
   
   
       11 - 12 . (canceled).  
   
   
       13 . The method of  claim 5 , wherein: 
 the common masking step comprises masking only portions of some of the devices which receive the halo implant;    said devices which receive the halo implant comprise NMOS field effect transistors having source regions and drain regions; and    said portions comprise portions of peripheral circuitry devices, wherein said masking comprises masking only one of the source region and drain region for one of the three devices, and exposing both of the source region and drain region for another of the three devices.    
   
   
       14 . (canceled).  
   
   
       15 . The method of  claim 5 , wherein: 
 the common masking step comprises masking only portions of some of the devices which receive the halo implant;    said devices which receive the halo implant comprise PMOS field effect transistors having source regions and drain regions; and    said portions comprise portions of peripheral circuitry devices, wherein said masking comprises masking only one of the source region and drain region for one of the three devices, and exposing both of the source region and drain region for another of the three devices.    
   
   
       16 - 49 . (canceled).  
   
   
       50 . A semiconductor processing method comprising implanting dopant through one common mask, implanting comprising conducting a halo implant of devices formed over a substrate comprising memory circuitry and peripheral circuitry sufficient to impart to at least three of the devices three different respective threshold voltages, the one common mask masking only portions of some of the devices which receive the halo implant, the devices receiving the halo implant comprising MOS field effect transistors having source regions and drain regions and the mask comprises a mask masking only one of the source region and drain region for one of the three devices, and exposing both of the source region and drain region for another of the three devices.  
   
   
       51 . The method of  claim 50 , wherein the three devices comprise peripheral circuitry.  
   
   
       52 . The method of  claim 50 , wherein the three devices comprise memory circuitry.  
   
   
       53 . The method of  claim 50 , wherein the three devices comprise NMOS field effect transistors.  
   
   
       54 . The method of  claim 50 , wherein the three devices comprise NMOS field effect transistors comprising peripheral circuitry.  
   
   
       55 . The method of  claim 50 , wherein the three devices comprise PMOS field effect transistors.  
   
   
       56 . The method of  claim 50 , wherein the three devices comprise PMOS field effect transistors comprising peripheral circuitry.  
   
   
       57 . The method of  claim 50 , further comprising, prior to implanting, a common masking act comprising masking only portions of some peripheral circuitry devices which receive the halo implant.  
   
   
       58 . The method of  claim 50 , further comprising, prior to implanting, a common masking act comprising masking only portions of some of the devices which receive the halo implant, wherein the devices which receive the halo implant comprise NMOS field effect transistors and wherein the portions comprise portions of peripheral circuitry devices.  
   
   
       59 . The method of  claim 50 , further comprising, prior to implanting, a common masking act comprising masking only portions of some of the devices which receive the halo implant, wherein the devices which receive the halo implant comprise PMOS field effect transistors and the portions comprise portions of peripheral circuitry devices.  
   
   
       60 . The method of  claim 50 , further comprising, prior to implanting, a common masking act comprising masking only portions of some of the devices which receive the halo implant, wherein the devices which receive the halo implant comprise NMOS field effect transistors and the portions comprise portions of peripheral and memory circuitry devices.