US2005042809A1PendingUtilityA1

Bottom gate-type thin-film transistor and method for manufacturing the same

Priority: Nov 7, 2000Filed: Sep 21, 2004Published: Feb 24, 2005
Est. expiryNov 7, 2020(expired)· nominal 20-yr term from priority
H10D 30/0321H10D 86/451H10D 86/60H10D 86/00H10D 30/6745H10D 30/6732H10D 30/6715H10D 30/0316G02F 1/136
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Claims

Abstract

In a bottom gate-type thin-film transistor manufacturing method, after ion doping, an ion stopper ( 55 ) is removed. The ion stopper ( 55 ) does not remain in the interlayer insulating film ( 8 ) lying immediately above the gate electrode. The thin-film transistor has such a structure that no ion stopper ( 55 ), and the interlayer insulating layer is in direct contact with at least the channel region of the semiconductor layer ( 4 ). The impurity concentration in the vicinity of the interface between the interlayer insulating film and the semiconductor layer 4 is 10 18 atoms/cc or less. This structure can prevent the back channel phenomenon and reduce variations in characteristic resulting from variations in manufacturing.

Claims

exact text as granted — not AI-modified
1 . A bottom gate-type thin-film transistor, comprising: 
 a gate electrode formed on a transparent insulating substrate;    a gate insulating film overlying said gate electrode;    a semiconductor layer formed on said gate insulating film, said semiconductor layer having a source region and a drain region doped with impurities, and a channel region; and    an interlayer insulating film formed on said semiconductor layer, wherein    in said interlayer insulating film, a region in a vicinity of at least an interface between at least said channel region in said semiconductor layer has an impurity concentration of 10 18  atom/cc or less.    
   
   
       2 . A bottom gate-type thin-film transistor, comprising: 
 a gate electrode formed on a transparent insulating substrate;    a gate insulating film overlying said gate electrode;    a semiconductor layer formed on said gate insulating film, said semiconductor layer having a source region, and a drain region, impurities being doped and a channel region; and    an interlayer insulating film formed on said semiconductor layer, wherein    both said interlayer insulating film and said semiconductor layer are in direct contact with each other and are disposed above said gate electrode.    
   
   
       3 - 5 . (Canceled)

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