US2005040505A1PendingUtilityA1
Substantially hermetic packages for semiconductor devices and substantially hermetically packaged, semiconductor devices
Priority: Aug 17, 2000Filed: Aug 31, 2004Published: Feb 24, 2005
Est. expiryAug 17, 2020(expired)· nominal 20-yr term from priority
Inventors:Warren M. Farnworth
H10W 72/551H10W 74/00H10W 90/756H10W 90/754H10W 72/9413H10W 72/0198H10W 72/951H10W 72/075H10W 90/724H10W 72/01331H10P 72/0441H10W 74/43H10W 70/415H10W 74/114H10W 74/111H10W 74/40H10W 74/014H10W 74/01B33Y 30/00B33Y 80/00B29C 70/72Y02P80/30G03F 7/70416B33Y 10/00
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Claims
Abstract
A package for a semiconductor device includes a plurality of adjacent, mutually adhered regions of substantially hermetic packaging material, such as thermoplastic glass, other types of glass, ceramic, or metal. These regions may be formed by programmed material consolidation processes, such as stereolithography. The package may be used to encapsulate a semiconductor device. The semiconductor device may be packaged before being physically separated from other semiconductor devices that were fabricated on the same substrate.
Claims
exact text as granted — not AI-modified1 . A packaged semiconductor device, comprising:
a connection element; at least one semiconductor die operably connected to the connection element; and a hermetic package substantially sealing at least a portion of the at least one semiconductor die from an external environment, the hermetic package comprising a plurality of adjacent, mutually adhered regions of a hermetic packaging material.
2 . The packaged semiconductor device of claim 1 , wherein the connection element comprises a carrier substrate.
3 . The packaged semiconductor device of claim 2 , wherein a surface of the at least one semiconductor die is disposed against the carrier substrate.
4 . The packaged semiconductor device of claim 3 , wherein the hermetic package covers at least another surface of the at least one semiconductor die.
5 . The packaged semiconductor device of claim 1 , wherein the connection element comprises a lead frame.
6 . The packaged semiconductor device of claim 5 , wherein the hermetic package covers at least the at least one semiconductor die.
7 . The packaged semiconductor device of claim 6 , wherein the hermetic package also covers a portion of the lead frame adjacent to the at least one semiconductor die.
8 . The packaged semiconductor device of claim 1 , wherein the hermetic packaging material comprises thermoplastic glass.
9 . The packaged semiconductor device of claim 1 , wherein the hermetic packaging material comprises ceramic or metal.
10 . The packaged semiconductor device of claim 1 , wherein the plurality of adjacent, mutually adhered regions comprises a plurality of at least partially superimposed layers.
11 . A substantially hermetically packaged semiconductor device, comprising:
a semiconductor die; and a package surrounding at least a portion of the semiconductor die and substantially hermetically sealing same, the package comprising a plurality of adjacent, mutually adhered regions comprising a thermoplastic glass.
12 . The semiconductor device of claim 11 , further comprising a carrier substrate connected to the semiconductor die.
13 . The semiconductor device of claim 1 1 , further comprising a lead frame connected to the semiconductor die and at least partially substantially hermetically sealed by the package.
14 . The semiconductor device of claim 11 , wherein the package further comprises at least one external circuit in communication with at least one bond pad of the semiconductor die.
15 . The semiconductor device of claim 1 1 , wherein the plurality of adjacent, mutually adhered regions comprises a plurality of at least partially superimposed layers.
16 . A package for substantially hermetically packaging a semiconductor device, comprising at least one portion, the at least one portion comprising a plurality of adjacent, mutually adhered regions comprising hermetic packaging material.
17 . The package of claim 16 , wherein the at least one portion includes a receptacle configured to receive at least a portion of the semiconductor device and to substantially seal a semiconductor die of the semiconductor device from an environment external to the package.
18 . The package of claim 16 , wherein the package further comprises another portion configured to be assembled with the at least one portion so as to substantially seal a semiconductor die of the semiconductor device from an environment external to the package.
19 . The package of claim 18 , wherein the another portion also comprises a plurality of adjacent, mutually adhered regions comprising hermetic packaging material.
20 . The package of claim 16 , wherein the hermetic packaging material comprises a thermoplastic glass.
21 . The package of claim 16 , wherein the hermetic packaging material comprises a ceramic or a metal.
22 . The package of claim 16 , wherein the plurality of adjacent, mutually adhered regions comprises a plurality of at least partially superimposed layers.Join the waitlist — get patent alerts
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