Fabrication of self-aligned bipolar transistor

Abstract

A method for fabricating a self-aligned bipolar transistor, wherein a substrate having an epitaxial layer formed thereon as a base is provided. After this, a first dielectric layer, a second dielectric layer are sequentially formed on the epitaxial layer, followed by forming an opening in the second dielectric layer. A conductive spacer is formed on the sidewall of the opening. Using the second dielectric layer and the conductive spacer as a mask, a first dielectric layer in the opening is removed. A conductive layer is then formed in the opening as an emitter, followed by completely removing the second dielectric layer. A doping is conducted on the emitter. Using the emitter and the conductive spacer as a mask, a part of the first dielectric layer is removed. Further using the emitter and the conductive spacer as a mask, another doping is conducted to form a part of the epitaxial layer as a base contact region.

1 . A method for fabricating a bipolar transistor, comprising the steps of: 
 providing a substrate having an epitaxial layer already formed thereon, wherein the epitaxial layer serves as a base;    forming sequentially a first dielectric layer, a second dielectric layer on the epitaxial layer;    forming an opening in the second dielectric layer;    forming a conductive spacer on a sidewall of the opening;    removing the first dielectric layer within the opening using the second dielectric layer and the conductive spacer as a mask;    forming a conductive layer in the opening;    removing the conductive layer outside the opening to form an emitter;    removing the second dielectric layer and a portion of the first dielectric layer to form a self-aligned bipolar transistor using the emitter and the conductive spacer as a mask; and    performing a doping step on the epitaxial layer to form an extrinsic epitaxial base contact area.    
   
   
       2 . The method of  claim 1 , wherein the substrate is formed with a material selected from the group consisting of silicon germanium, silicon, gallium arsenide and indium phosphide.  
   
   
       3 . The method of  claim 1 , wherein the epitaxial layer comprises a material selected from the group consisting of silcion germanium, silicon, gallium arsenide and indium phosphide, an alloy of aluminum-gallium arsenide (Al x Ga 1-x As, x≦1) and an alloy of indium-gallium arsenide (In x Ga 1-x As, x≦1).  
   
   
       4 . The method of  claim 1 , wherein the conductive spacer is doped polysilicon. doped gallium arsenide, doped indium phosphid, tungsten silicide, tungsten, titanium or titanium nitride.  
   
   
       5 . The method of  claim 1 , wherein the conductive spacer and the conductive layer have a high etch selectivity to the first dielectric layer and the second dielectric layer.  
   
   
       6 . The method of  claim 1 , wherein the first dielectric layer and the second dielectric layer have a high etch selectivity.  
   
   
       7 . The method of  claim 6 , wherein the first dielectric layer is formed with a material selected from the group consisting of undoped silicon glass, borophosphosilicate glass, phosphosilicate glass, silicon rich oxide and fluorinated silicon glass.  
   
   
       8 . The method of  claim 6 , wherein the second dielectric layer is formed with a material selected from the group consisting of silicon nitride, oxynitride and silicon carbide.  
   
   
       9 . The method of  claim 1 , wherein the conductive layer is formed with polysilicon, gallium arsenide, or indium phosphide.  
   
   
       10 . The method of  claim 1 , wherein forming the conductive layer into the opening comprises: 
 depositing a conductive layer and filling the opening; and    removing a part of the conductive layer outside the opening.    
   
   
       11 . The method of  claim 10 , wherein removing the part of the conductive layer outside the opening comprises performing chemical mechanical polishing or etching back.  
   
   
       12 . The method of  claim 1  further comprising a doping process on the emitter to reduce a resistivity of the emitter.  
   
   
       13 . The method of  claim 1 , wherein a dopant type of the base is different from a dopant type of the emitter and the collector.  
   
   
       14 . The method of  claim 1  further comprising forming a dielectric spacer around the emitter.  
   
   
       15 . The method of  claim 1  further comprising forming a self-aligned silicide on both the emitter and the extrinsic base contact area.  
   
   
       16 . The method of  claim 1  further comprising a rapid thermal annealing process to activate dopants and eliminate a doping defect.  
   
   
       17 . A self-aligned bipolar transistor, comprising: 
 a substrate served as a collector;    a self-aligned base located on the substrate;    an extrinsic base contact region located on the substrate and both sides of the self-aligned base; and    an emitter positioned on a top of the self-aligned base, wherein the emitter serves as a hard mask to define the self aligned base.    
   
   
       18 . The self-aligned bipolar transistor of  claim 17  further comprising a conductive spacer positioned on a top part of a sidewall of the emitter.  
   
   
       19 . The self-aligned bipolar transistor of  claim 17  further comprising a dielectric layer between the conductive spacer and the self-aligned base.  
   
   
       20 . The self aligned bipolar transistor of  claim 17  further comprising a dielectric spacer around the emitter.  
   
   
       21 . The self aligned bipolar transistor of  claim 17  further comprising a self-aligned silicide layer on the emitter and the extrinsic base contact region.  
   
   
       22 . The self aligned bipolar transistor of  claim 17 , wherein the self-aligned base comprises a non-selective epitaxial film.  
   
   
       23 . The self aligned bipolar transistor of  claim 17 , wherein the emitter further comprises a predetermined resistivity provided by a doping process.  
   
   
       24 . The self aligned bipolar transistor of  claim 17 , wherein the extrinsic base contact further comprises a predetermined resistivity provided by a doping process.  
   
   
       25 . The self-aligned bipolar transistor of  claim 17 , wherein the substrate is formed with a material selected form the group consisting of silicon germanium, silicon, gallium arsenide and indium phosphide.  
   
   
       26 . The self aligned bipolar transistor of  claim 17 , wherein the base is formed with a material selected from the group consisting of silicon germanium, silicon, gallium arsenide, indium phosphide, an alloy of aluminum-gallium arsenide (Al x Ga 1-x As, x≦1) and an alloy of indium-gallium arsenide (In x Ga 1-x As, x≦1).  
   
   
       27 . The self aligned bipolar transistor of  claim 17 , wherein the emitter is formed with a material selected from the group consisting of polysilicon, gallium arsenide and indium phosphide.  
   
   
       28 . The self aligned bipolar transistor of  claim 17 , wherein the conductive spacer comprises polysilicon, gallium arsenide, indium phosphide, tungsten silicide, tungsten, titanium and titanium nitride.  
   
   
       29 . A fabrication method for a self-aligned bipolar transistor, comprising: 
 providing a substrate having an epitaxial layer already formed thereon as a base;    forming sequentially a first dielectric layer, a second dielectric layer, a third dielectric layer and a fourth dielectric layer on the substrate;    forming an opening in the fourth dielectric layer;    forming a conductive spacer on a sidewall of the opening;    removing the third dielectric layer, the second dielectric layer and the first dielectric layer within the opening using the fourth dielectric layer and the conductive spacer as a mask;    forming a conductive layer on the fourth dielectric layer and to fill the opening;    removing the conductive layer outside the opening to form an emitter; and    fully removing the first, the second, the third and the fourth dielectric layers to form a self-aligned bipolar transistor using the emitter and the conductive spacer as a mask.    
   
   
       30 . The method of  claim 29  further comprising performing a first doping on the emitter.  
   
   
       31 . The method of  claim 29  further comprising performing a second doping on the epitaxial layer to form an extrinsic base contact area.  
   
   
       32 . The method of  claim 29 , wherein the substrate is formed with a material selected from the group consisting of silicon germanium, silicon, gallium arsenide and indium phosphide.  
   
   
       33 . The method of  claim 29 , wherein the epitaxial layer is formed with a material selected from the group consisting of silicon germanium, silicon, gallium arsenide and indium phosphide, an alloy of aluminum-gallium arsenide (Al x Ga 1-x As, x≦1) and an alloy of indium-gallium arsenide (In x Ga 1-x As, x≦1).  
   
   
       34 . The method of  claim 29 , wherein the conductive spacer is formed with a material consisting of polysilicon, doped gallium arsenide, doped indium phosphide, tungsten silicide, tungsten, titanium and titanium nitride.  
   
   
       35 . The method of  claim 29 , wherein the conductive spacer has a high etch selectivity to the first dielectric layer, the second dielectric layer, the third dielectric layer and the fourth dielectric layer.  
   
   
       36 . The method of  claim 29 , wherein the first dielectric layer and the second dielectric layer have a high etch selectivity.  
   
   
       37 . The method of  claim 29 , wherein the second dielectric layer and the third dielectric layer have a high etch selectivity.  
   
   
       38 . The method of  claim 29 , wherein the third dielectric layer and the fourth dielectric layer have a high etch selectivity.  
   
   
       39 . The method of  claim 29 , wherein the first dielectric layer and the third dielectric layer are formed with materials selected from the group consisting of undoped silicon glass, borophosphosilicate glass, phosphosilicate glass, silicon rich oxide and fluorinated silicon glass.  
   
   
       40 . The method of  claim 29 , wherein the second dielectric layer and the fourth dielectric layer are formed with materials selected from the group consisting of silicon nitride, silicon oxynitride and silicon carbide.  
   
   
       41 . The method of  claim 29  further comprising forming a dielectric spacer around the emitter.  
   
   
       42 . The method of  claim 29  further comprising forming a salicide layer on the emitter and the extrinsic base contact area.  
   
   
       43 . A structure of a self-aligned bipolar transistor, the structure comprising: 
 a substrate served as a collector;    a self aligned base positioned on the substrate;    an extrinsic base contact region positioned on the substrate beside two sides of the base;    an emitter disposed on the base;    a conductive spacer disposed on an upper sidewall of the emitter;    a first dielectric layer disposed on the base and beside two sides of the emitter and extended to a part of the base contact region;    a second dielectric layer disposed on the first dielectric layer; and    a third dielectric layer disposed on an emitter sidewall between the conductive spacer and the second dielectric layer, wherein edges of the third dielectric layer align with edges of the base.    
   
   
       44 . The structure of  claim 43 , wherein the substrate is formed with a material selected from the group consisting of silicon germanium, silicon, gallium arsenide and indium phosphide.  
   
   
       45 . The structure of  claim 43  further comprising a dielectric spacer, wherein the dielectric spacer is located on sidewalls of the conductive spacer and the third dielectric layer and edges of the spacer approximately align with edges of the first and the second dielectric layer.  
   
   
       46 . The structure of  claim 43  further comprising a self-aligned silicide layer, wherein the silicide layer is disposed on the emitter, the conductive spacer and the extrinsic base contact region.  
   
   
       47 . The structure of  claim 46 , wherein the self-aligned silicide layer is formed with a material selected from the group consisting of nickel salicide, cobalt salicide and titanium salicide.  
   
   
       48 . The structure of  claim 43 , wherein the base is formed with a material selected from the group consisting of silicon germanium, silicon, gallium arsenide and indium phosphide, an alloy of aluminum-gallium arsenide (Al x Ga 1-x As, x≦1) and an alloy of indium-gallium arsenide (In x Ga 1-x As, x≦1).  
   
   
       49 . The structure of  claim 43 , wherein the emitter is formed with a material selected from the group consisting of polysilicon, gallium arsenide and indium phosphide.  
   
   
       50 . The structure of  claim 43 , wherein the conductive spacer is formed with a material selected from the group consisting of polysilicon, gallium arsenide and indium phosphide, tungsten silicide, tungsten, titanium, titanium nitride.  
   
   
       51 . The structure of  claim 43 , wherein first dielectric layer and the second dielectric layer have a high etch selectivity.  
   
   
       52 . The structure of  claim 43 , wherein the second dielectric layer and the third dielectric layer have a high etch selectivity.  
   
   
       53 . The structure of  claim 43 , wherein the first dielectric layer is formed with a material selected from the group consisting of undoped silicon glass, borophosphosilicate glass, phosphosilicate glass, silicon rich oxide and fluorinated silicon glass.  
   
   
       54 . The structure of  claim 43 , wherein the second dielectric layer is formed with a material selected from the group consisting of silicon nitride, oxynitride and silicon carbide.  
   
   
       55 . The structure of  claim 43 , wherein the third dielectric layer is formed with a material selected from the group consisting of undoped silicon glass, borophosphosilicate glass, phosphosilicate glass, silicon rich oxide and fluorinated silicon glass.  
   
   
       56 . The structure of  claim 43 , wherein the emitter further comprises a predetermined resistivity provided by a doping process.  
   
   
       57 . The structure of  claim 43 , wherein the extrinsic base contact region further comprises a predetermined resistivity provided by a doping process.