Transistor structures and processes for forming same

Abstract

Source drain on insulator (SDOI) transistors and methods of forming SDOI transistors are described. The SDOI transistors are formed to provide electrical isolation between the body and the channel of the transistor. The electrical isolation comprises either a depletion layer or a p-n junction formed below the SDOI transistor channel region that spans laterally between the SDOI insulators.

1 . A transistor structure for a semiconductor assembly comprising: 
 first and second laterally spaced insulative regions having source and drain regions residing above the first and second laterally spaced insulative regions respectively, such that a transistor channel region extends laterally between the first and second laterally spaced insulative regions; and    an electrical isolation region at the base of the first and second laterally spaced insulative regions, the electrical isolation region comprising a conductive depletion region laterally spanning completely between the first and second laterally spaced insulative regions.    
   
   
       2 . The transistor structure of  claim 1 , wherein the transistor structure comprises a p-channel transistor with the conductive depletion region having a p-type conductivity.  
   
   
       3 . The transistor structure of  claim 1 , wherein the transistor structure comprises an n-channel transistor with the conductive depletion region having an n-type conductivity.  
   
   
       4 . A transistor structure for a semiconductor assembly comprising: 
 first and second laterally spaced insulative regions having source and drain regions residing above the first and second laterally spaced insulative regions respectively, such that a transistor channel region extends laterally between the first and second laterally spaced insulative regions; and    an electrical isolation region at the base of the first and second laterally spaced insulative regions, the electrical isolation region comprising a p-n junction laterally spanning completely between the first and second laterally spaced insulative regions.    
   
   
       5 . The transistor structure of  claim 4 , wherein the transistor structure comprises a p-channel transistor.  
   
   
       6 . The transistor structure of  claim 4 , wherein the transistor structure comprises an n-channel transistor.  
   
   
       7 . A p-channel Source-drain On Insulator (SDOI) transistor structure for a semiconductor assembly comprising: 
 first and second laterally spaced insulative regions having p-type source and drain regions residing above the first and second laterally spaced insulative regions respectively, such that a transistor channel region extends laterally between the first and second laterally spaced insulative regions; and    an electrical isolation region at the base of the first and second laterally spaced insulative regions, the electrical isolation region comprising a p-type conductive depletion region laterally spanning completely between the first and second laterally spaced insulative regions.    
   
   
       8 . An n-channel Source-drain On Insulator (SDOI) transistor structure for a semiconductor assembly comprising: 
 first and second laterally spaced insulative regions having n-type source and drain regions residing above the first and second laterally spaced insulative regions respectively, such that a transistor channel region extends laterally between the first and second laterally spaced insulative regions; and    an electrical isolation region at the base of the first and second laterally spaced insulative regions, the electrical isolation region comprising an n-type conductive depletion region laterally spanning completely between the first and second laterally spaced insulative regions.    
   
   
       9 . A p-channel Source-drain On Insulator (SDOI) transistor structure for a semiconductor assembly comprising: 
 first and second laterally spaced insulative regions having p-type source and drain regions residing above the first and second laterally spaced insulative regions respectively, such that a transistor channel region extends laterally between the first and second laterally spaced insulative regions; and    an electrical isolation region at the base of the first and second laterally spaced insulative regions, the electrical isolation region comprising a p-n junction laterally spanning completely between the first and second laterally spaced insulative regions.    
   
   
       10 . An n-channel Source-drain On Insulator (SDOI) transistor structure for a semiconductor assembly comprising: 
 first and second laterally spaced insulative regions having n-type source and drain regions residing above the first and second laterally spaced insulative regions respectively, such that a transistor channel region extends laterally between the first and second laterally spaced insulative regions; and    an electrical isolation region at the base of the first and second laterally spaced insulative regions, the electrical isolation region comprising a p-n junction laterally spanning completely between the first and second laterally spaced insulative regions.    
   
   
       11 . A p-channel Source-drain On Insulator (SDOI) transistor structure for a semiconductor assembly comprising: 
 first and second laterally spaced insulative regions having p-type source and drain regions residing above the first and second laterally spaced insulative regions respectively, such that an transistor channel region extends laterally between the first and second laterally spaced insulative regions; and    a boron doped conductive depletion region laying beneath the transistor channel region and laterally spanning completely between the bases of the first and second laterally spaced insulative regions.    
   
   
       12 . An n-channel Source-drain On Insulator (SDOI) transistor structure for a semiconductor assembly comprising: 
 first and second laterally spaced insulative regions having n-type source and drain regions residing above the first and second laterally spaced insulative regions respectively, such that a transistor channel region extends laterally between the first and second laterally spaced insulative regions; and    an arsenic or phosphorus doped conductive depletion region laying beneath the transistor channel region and laterally spanning completely between the bases of the first and second laterally spaced insulative regions.    
   
   
       13 . A p-channel Source-drain On Insulator (SDOI) transistor structure for a semiconductor assembly comprising: 
 first and second laterally spaced insulative regions having source and drain regions residing above the first and second laterally spaced insulative regions respectively, such that a transistor channel region extends laterally between the first and second laterally spaced insulative regions; and    a p-n junction comprising boron and arsenic doped region laying beneath the transistor channel region and laterally spanning completely between the bases of the first and second laterally spaced insulative regions.    
   
   
       14 . An n-channel Source-drain On Insulator (SDOI) transistor structure for a semiconductor assembly comprising: 
 first and second laterally spaced insulative regions having source and drain regions residing above the first and second laterally spaced insulative regions respectively, such that a transistor channel region extends laterally between the first and second laterally spaced insulative regions; and    a p-n junction comprising boron and arsenic doped region laying beneath the transistor channel region and laterally spanning completely between the bases of the first and second laterally spaced insulative regions.