US2005040461A1PendingUtilityA1

Semiconductor device

Priority: Sep 5, 2002Filed: Sep 29, 2004Published: Feb 24, 2005
Est. expirySep 5, 2022(expired)· nominal 20-yr term from priority
H10D 64/01344H10D 64/01342H10D 30/62H10D 30/60H10D 84/856H10D 84/0181H10D 84/0149H10D 84/0144H10D 84/0142H10D 84/83H10D 84/038H10D 64/693H10D 64/691H10D 64/685
41
PatentIndex Score
0
Cited by
0
References
0
Claims

Abstract

A semiconductor device comprises a semiconductor substrate, a first circuit formed on the substrate, and a second circuit connected to the first circuit as an input/output portion thereof and powered by a voltage higher than that for the first circuit, the first circuit including a first and a second field-effect transistor, the first drain region of the first transistor accompanying a first load capacitance, the second drain region of the second transistor accompanying a second load capacitance smaller than the first load capacitance, and the first gate insulation film of the first transistor having an average relative dielectric constant higher than that of the second gate insulation film of the second transistor, thereby realizing a high operation speed.

Claims

exact text as granted — not AI-modified
1 - 10 . (Cancel)  
   
   
       11 . A manufacturing method of a first and a second field-effect transistors comprising: 
 disposing a plurality of isolation regions in a semiconductor substrate to define first and second well forming regions;    implanting an impurity of a first conductivity type into the first and the second well forming regions to form first and second well regions of the first conductivity type;    forming a gate insulation film in a surface of the first and the second well regions;    selectively forming a nitrogen diffusion preventive film on the gate insulation film of the first well region;    exposing the first and the second well regions to a nitrogen-containing atmosphere;    after removing the nitrogen diffusion preventive film, forming a polycrystalline silicon film on the gate insulation film on the first and the second well regions;    selectively and anisotropically etching the polycrystalline silicon film to form first and second gate electrodes on the gate insulation film on the first and the second well regions; and    forming first and second pair of source/drain regions by implanting and thermally diffusing an impurity of a second conductivity type in the first and the second well regions, using the first and the second gate electrodes as masks, respectively.    
   
   
       12 . The manufacturing method according to  claim 11 , wherein the gate insulation film includes silicon, oxide, and a metal element.  
   
   
       13 . The manufacturing method according to  claim 12 , wherein the forming of a first and a second pair of source/drain regions includes precipitating an oxide of the metal element in the gate insulation film on the first well region.  
   
   
       14 . A manufacturing method of a first and a second field-effect transistors comprising: 
 forming first and second well forming regions separated by a plurality of isolation regions in a semiconductor substrate;    forming first and second well regions of a first conductivity type by implanting an impurity of a first conductivity type into the first and the second well forming regions;    forming a first gate insulation film on the first and the second well regions;    introducing nitrogen into the first gate insulation film by exposing the first gate insulation film to a nitrogen-containing atmosphere;    selectively removing the first gate insulation film on the first well region;    newly forming a second gate insulation film on the first well region;    forming a polycrystalline silicon film on the first and the second well regions via the first and the second gate insulation films;    forming first and second gate electrodes above the first and the second well regions by selectively and anisotropically etching the polycrystalline silicon film; and    forming a first and a second pair of source/drain regions by implanting and thermally diffusing an impurity of a second conductivity type into the first and the second well regions, using the first and the second gate electrodes as masks, respectively.    
   
   
       15 . The manufacturing method according to  claim 14 , wherein the first and the second gate insulation film include silicon, oxygen, and a metal element.  
   
   
       16 . The manufacturing method according to  claim 15 , wherein the forming of a first and a second pair of source/drain regions includes precipitating an oxide of the metal element in the gate insulation film on the first well region.  
   
   
       17 . A manufacturing method of a first and a second field-effect transistors comprising: 
 forming a first and a second well forming region separated by a plurality of isolation regions in a semiconductor substrate;    forming a first and a second well regions of a first conductivity type by implanting an impurity of a first conductivity type into the first and the second well forming regions;    forming a first gate insulation film on the first and the second well regions;    selectively forming a nitrogen diffusion preventive film above the surface of the first well region;    removing the first gate insulation film on the second well region by using the nitrogen diffusion preventive film as a mask;    newly forming a second gate insulation film on the first and the second well regions;    introducing nitrogen into the second gate insulation film;    removing the second gate insulation film and the nitrogen diffusion preventive film on the first well region;    after removing the nitrogen diffusion preventive film, forming a polycrystalline silicon film on the first and the second well regions via the first and the second gate insulation films;    forming a first and a second gate electrodes above the first and the second well regions by selectively and anisotropically etching the polycrystalline silicon film; and    forming a first and a second pair of source/drain regions by implanting and thermally diffusing an impurity of a second conductivity type into the first and the second well regions, using the first and the second gate electrodes as masks, respectively.    
   
   
       18 . The manufacturing method according to  claim 17 , wherein the first and the second gate insulation films includes silicon, oxygen, and a metal element.  
   
   
       19 . The manufacturing method according to  claim 18 , wherein the forming step of a first and a second pair of source/drain regions includes precipitating an oxide of the metal element in the gate insulation film on the first well region.  
   
   
       20 . A manufacturing method of a first and a second field-effect transistors comprising: 
 forming a first and a second well forming regions separated by a plurality of isolation regions in a semiconductor substrate;    forming a first and a second well regions of a first conductivity type by implanting an impurity of a first conductivity type into the first and the second well forming regions;    forming a first gate insulation film on the first and the second well regions;    removing the first gate insulation film on the second well region;    newly forming a second gate insulation film on the second well region;    forming a polycrystalline silicon film on the first and the second well regions via the first and the second gate insulation films;    forming a first and a second gate electrodes above the first and the second well regions by selectively and anisotropically etching the polycrystalline silicon film; and    forming a first and a second pair of source/drain regions by implanting and thermally diffusing an impurity of a second conductivity type into the first and the second well regions, using the first and the second gate electrodes as masks, respectively.

Join the waitlist — get patent alerts

Track US2005040461A1 — get alerts on status changes and closely related new filings.

We store only your email — no account needed. See our privacy policy.