Apparatus and method for co-simulating processors and DUT modules

Abstract

An apparatus and method for co-simulating of processors and DUT modules comprising steps of constructing and executing a processor simulation program and a Hardware Description Language (HDL) simulation environment that is activated by a corresponding simulator, and further for executing a command processing model and the processor simulation program, and establishing a message queue as a buffer of the message and data. Whenever the intercommunication occurred, the command will be processed via a Program Language Interface (PLI), the command processing model, a message queue mechanism for I/O command, and a signal mechanism for interrupt command.

1 . An apparatus for co-simulating of processors and DUT modules comprising: 
 a Hardware Description Language (HDL) simulation environment for providing a performing environment for at least a DUT module coupled to at least a processor, wherein said HDL simulation environment constructed in a HDL and performed by a simulator;    at least a processor simulation program for simulating functions of said processors, wherein said processor simulation program constructed in a programming language differs from said HDL; and    a DUT module for interacting with said processor simulation program, wherein said DUT module constructed in said HDL and indicating the peripheral devices coupled to said processor.    
   
   
       2 . The apparatus as recited in  claim 1 , further comprising: 
 a compiler for compiling said processor simulation program, wherein said compiler installed in a same platform of said processor simulation program.    
   
   
       3 . The apparatus as recited in  claim 2 , wherein said same platform is an Unix-like workstation.  
   
   
       4 . The apparatus as recited in  claim 1 , further comprising: 
 a process number for identifying processes under a multi-processor and a multi-task architecture; and    a message queue for storing the messages of co-simulating of processors and DUT modules.    
   
   
       5 . The apparatus as recited in  claim 1 , wherein said HDL simulation environment further comprising: 
 a command processing model for providing a interface to process interaction of said processor simulation program and said DUT module.    
   
   
       6 . The apparatus as recited in  claim 5 , wherein said HDL selected form the group consisting of Verilog and VHDL.  
   
   
       7 . The apparatus as recited in  claim 5 , wherein said HDL simulation environment further comprising: 
 a Programming Language Interface (PLI) for providing a library for function call from said HDL simulation environment and said processor simulation program.    
   
   
       8 . The apparatus as recited in  claim 1 , wherein said simulator selected form the group consisting of Verilog-XL and NC-Verilog.  
   
   
       9 . A method for co-simulating of processors and DUT modules comprising: 
 constructing and performing a HDL simulation environment constructed in a HDL;    constructing a processor simulation program in a programming language differs from said HDL;    constructing a DUT module in said HDL; and    performing said processor simulation program and said DUT model for simulating processors and DUT modules.    
   
   
       10 . The method as recited in  claim 9 , further comprising: 
 generating a process number for identifying processes under a multi-processor and a multi-task architecture.    
   
   
       11 . The method as recited in  claim 9 , further comprising: 
 utilizing a library of a PLI provided by said HDL and a message queue mechanism to perform and access messages; and    utilizing said library and a signal mechanism to process the interrupt messages.    
   
   
       12 . The method as recited in  claim 9 , wherein said processor simulation program and said DUT model is performed in a same platform of Unix-like workstation.  
   
   
       13 . The method as recited in  claim 9 , further comprising: 
 constructing a command processing model for providing a interface to process interaction of said processor simulation program and said DUT module.    
   
   
       14 . A method for verifying a design of a peripheral device comprising: 
 constructing a processor simulation program in a first program language;    constructing an interface model program in a second program language differs from said first program language, wherein said second program language is a HDL;    constructing a peripheral device program in said second program language; and    performing said interface model program for simulating interaction of processors and said peripheral device in a workstation platform.