Apparatus and method for self testing programmable logic arrays

Abstract

A self-testing programmable logic array PLA system has an array of programmably interconnected logic cells, a built-in self-test (BIST) structure interconnected with the logic cells, and a BIST engine having an initiation input. The system is characterized in that, upon receiving the initiation input, the BIST engine drives the BIST structure to test connections and functions of the PLA. BIST systems are taught for stand-alone programmable logic arrays (PLAs) and for PLAs embedded in System-on-a-Chip (SoC) devices.

1 . A programmable logic array (PLA) system comprising: 
 an array of programmably interconnected logic cells forming a core and edges;    global signal lines configured to carry global signals from at least the edges to the core of the array;    a group addressing block configured to program some of the programmably interconnected logic cells with an identical pattern;    a group compare block configured to compare outputs of some of the programmably interconnected logic cells; and    a built-in self-test (BIST) engine configured to generate first signals to configure the array of programmably interconnected logic cells and drive the group addressing block and the group compare block to test memory, programmable interconnections, and functional logic of the programmably interconnected logic cells.    
   
   
       2 . The PLA system of  claim 1  wherein the global signal lines are from sources external from the PLA system.  
   
   
       3 . The PLA system of  claim 1  wherein the BIST engine generates a test-result output that indicates whether a test of the PLA system passed or failed.  
   
   
       4 . The PLA system of  claim 1  wherein the BIST engine receives a clock signal and an enable signal and wherein the BIST engine drives the group addressing block and the group compare block based on the clock signal and enable signal.  
   
   
       5 . The PLA system of  claim 1  wherein the BIST engine accumulates results of each test of the programmably interconnected logic cells under test.  
   
   
       6 . The PLA system of  claim 1  wherein the BIST engine generates a done signal to indicate a test is completed.  
   
   
       7 . The PLA system of  claim 1  wherein the BIST engine generates a go signal to indicate whether the array of programmably interconnected logic cells is fully functional.  
   
   
       8 . The PLA system of  claim 1  wherein the BIST engine comprises a microprocessor.  
   
   
       9 . The PLA system of  claim 1  wherein the BIST engine comprises a state machine.  
   
   
       10 . The PLA system of  claim 1  wherein the BIST engine is part of same integrated circuit structure as the array of programmably interconnected logic cells.  
   
   
       11 . The PLA system of  claim 1  wherein the BIST engine is implemented separately from the array of programmably interconnected logic cells.  
   
   
       12 . A system-on-a-chip (SoC) comprising: 
 multiple functional regions; and    a programmable logic array (PLA) system comprising an array of programmably interconnected logic cells forming a core and edges, global signal lines configured to carry global signals from at least the edges to the core of the array, a group addressing block configured to program some of the programmably interconnected logic cells with an identical pattern, a group compare block configured to compare outputs of some of the programmably interconnected logic cells, and a built-in self-test (BIST) engine configured to generate first signals to configure the array of programmably interconnected logic cells and drive the group addressing block and the group compare block to test memory, programmable interconnections, and functional logic of the programmably interconnected logic cells.    
   
   
       13 . The SoC system of  claim 12  wherein the global signal lines are from sources external from the PLA system.  
   
   
       14 . The SoC system of  claim 12  wherein the BIST engine generates a test-result output that indicates whether a test of the PLA system passed or failed.  
   
   
       15 . The SoC system of  claim 12  wherein the BIST engine receives a clock signal and an enable signal and wherein the BIST engine drives the group addressing block and the group compare block based on the clock signal and enable signal.  
   
   
       16 . The SoC system of  claim 12  wherein the BIST engine accumulates results of each test of the programmably interconnected logic cells under test.  
   
   
       17 . The SoC system of  claim 12  wherein the BIST engine generates a done signal to indicate a test is completed.  
   
   
       18 . The SoC system of  claim 12  wherein the BIST engine generates a go signal to indicate whether the array of programmably interconnected logic cells is fully functional.  
   
   
       19 . The SoC system of  claim 12  wherein the BIST engine comprises a microprocessor.  
   
   
       20 . The SoC system of  claim 12  wherein the BIST engine comprises a state machine.  
   
   
       21 . The SoC system of  claim 12  wherein the BIST engine is part of same integrated circuit structure as the array of programmably interconnected logic cells.  
   
   
       22 . The SoC system of  claim 12  wherein the BIST engine is implemented separately from the array of programmably interconnected logic cells.  
   
   
       23 . A method of operating a programmable logic array (PLA) system, the method comprising: 
 in a built-in self-test (BIST) engine, generating first signals to configure an array of programmably interconnected logic cells that form a core and edges;    in the BIST engine, driving the group addressing block and the group compare block to test memory, programmable interconnections, and functional logic of the programmably interconnected logic cells;    carrying global signals over global signal lines from at least the edges to the core of the array;    in a group addressing block, programming some of the programmably interconnected logic cells with an identical pattern; and    in a group compare block, comparing outputs of some of the programmably interconnected logic cells.    
   
   
       24 . The method of  claim 23  further comprising in the BIST engine, generating a test-result output that indicates whether a test of the PLA system passed or failed.  
   
   
       25 . The method of  claim 23  further comprising in the BIST engine, receiving a clock signal and an enable signal and wherein driving the group addressing block and the group compare block is based on the clock signal and enable signal.  
   
   
       26 . The method of  claim 23  further comprising in the BIST engine, accumulating results of each test of the programmably interconnected logic cells under test.  
   
   
       27 . The method of  claim 23  further comprising in the BIST engine, generating a done signal to indicate a test is completed.  
   
   
       28 . The method of  claim 23  further comprising in the BIST engine, generating a go signal to indicate whether the array of programmably interconnected logic cells is fully functional.