Processor with instructions that operate on different data types stored in the same single logical register file

Abstract

A processor with instructions to operate on different data types stored in a single logical register file. According to one embodiment of the invention, a processor includes a number of physical registers, a memory unit, and a decode/execution unit. The memory unit is to make the number of physical registers appear to software as a single software-visible register file. The decode/execution unit is to execute on the contents of the single software-visible register file instructions of a first instruction type and of a second instruction type, wherein the single software-visible register file is to be operated as a flat register file during execution of instructions of the second instruction type and as a stack referenced register file during execution of instructions of the first instruction type.

1 . A processor comprising: 
 a plurality of physical registers;    a memory unit to make said plurality of physical registers appear to software as a single software-visible register file; and    a decode/execution unit to execute on the contents of said single software-visible register file instructions of a first instruction type and of a second instruction type, wherein said single software-visible register file is to be operated as a flat register file during execution of instructions of said second instruction type and as a stack referenced register file during execution of instructions of said first instruction type.    
     
     
         2 . The processor of  claim 1 , further comprising: 
 a plurality of tags, corresponding to said single software-visible register file, to identify whether registers in said single software-visible register file are empty or non-empty; and    a tag modifier unit to alter said plurality of tags to indicate non-empty sometime between execution of instructions of said second instruction type and completion of execution of the next instruction of said first instruction type to be executed.    
     
     
         3 . The processor of  claim 2 , wherein said tag modifier unit is to alter said plurality of tags in response to either the execution of instructions of said second instruction type or an attempted execution of the next instruction of said first instruction type to be executed.  
     
     
         4 . The processor of  claim 2 , wherein said tag modifier unit is to alter said plurality of tags in between execution of instructions of said second instruction type and the execution of the next instruction of said first instruction type.  
     
     
         5 . The processor of  claim 2 , wherein said tag modifier unit is to alter said plurality of tags in response to an attempted execution of the first one of the instructions of said second instruction type to be executed since execution of instructions of said first instruction type.  
     
     
         6 . The processor of  claim 1 , further comprising: 
 a plurality of tags, corresponding to said single software-visible register file, to identify whether registers in said single software-visible register file are empty or non-empty; and    a tag modifier unit to alter said plurality of tags to indicate empty sometime between execution of a most recent instruction of said second type to be executed prior to execution of a next instruction of said first instruction type and attempted execution of said next instruction of said first instruction type to be executed since execution of said most recent instruction of said second instruction type.    
     
     
         7 . The processor of  claim 6 , wherein said tag modifier unit is to alter said plurality of tags to indicate empty responsive to execution of the most recent instruction of said second instruction type to be executed prior to execution of the next instruction of said first instruction type.  
     
     
         8 . The processor of  claim 6 , wherein said tag modifier unit is to alter said plurality of tags to indicate empty in response to said attempted execution.  
     
     
         9 . The processor of  claim 2 , wherein said tag modifier unit is to alter said plurality of tags in response to execution of each instruction in said second instruction type.  
     
     
         10 . The processor of  claim 1 , further comprising a status register having a top of stack field to identify one register in said single software-visible register file as a current top of stack register and to be altered to an initialization value sometime between execution of instructions of said second instruction type and a completion of execution of the next instruction of said first instruction type.  
     
     
         11 . The processor of  claim 1 , wherein each register in said single software-visible register file further comprises a sign and exponent field in which is to be written a value to indicate either not a number or infinity sometime between execution of instructions of said second instruction type and said execution of the next instruction of said first instruction type.  
     
     
         12 . The processor of  claim 1 , wherein said single software-visible register file is to contain data to be copied into a memory during execution of the next instruction of said first instruction type to be executed since execution of instructions of said second instruction type.  
     
     
         13 . The processor of  claim 1 , wherein execution of instructions of said second instruction type cause said processor to perform packed operations.  
     
     
         14 . The processor of  claim 1 , wherein execution of instructions of said second instruction type cause said processor to perform packed integer operations.  
     
     
         15 . The processor of  claim 1 , wherein execution of instructions of said second instruction type cause said processor to perform packed floating point operations.  
     
     
         16 . The processor of  claim 1 , wherein execution of instructions of said first instruction type cause said processor to perform floating point operations.  
     
     
         17 . The processor of  claim 1 , wherein execution of instructions of said first instruction type cause said processor to perform scalar operations.  
     
     
         18 . The processor of  claim 1 , wherein execution of instructions of said first instruction type cause said processor to perform scalar floating point operations.  
     
     
         19 . The processor of  claim 1 , wherein execution of instructions of said first and second instruction type respectively cause said processor to perform scalar and packed operations.  
     
     
         20 . The processor of  claim 19 , wherein said packed operations include integer operations, and said scalar operations include floating point operations.  
     
     
         21 . The processor of  claim 20 , wherein said packed operations also include floating point operations.  
     
     
         22 . A processor comprising: 
 a plurality of physical registers;    a memory unit to make said plurality of physical registers appear to software as an at least partially aliased single software-visible register file;    a decode/execution unit to execute on the contents of said single software-visible register file both packed data instructions and scalar data instructions;    a plurality of tags, corresponding to said single software-visible register file, to identify whether registers in said single software-visible register file are empty or non-empty; and    a tag modifier unit to alter, those tags of said plurality of tags that correspond to aliased registers, to indicate non-empty sometime between execution of one or more of said packed data instructions and completion of execution of the next one of said scalar data instructions.    
     
     
         23 . The processor of  claim 22 , wherein said single software-visible register file is to be operated as a fixed register file during execution of said packed data instructions and as a stack referenced register file during execution of said scalar data instructions.  
     
     
         24 . The processor of  claim 22 , wherein said processor is to perform packed integer operations during execution of said packed data instructions and to perform scalar floating point operations during execution of said scalar data instructions.  
     
     
         25 . The processor of  claim 24 , wherein said processor is also to perform packed floating point operations during execution of said packed data instructions.  
     
     
         26 . The processor of  claim 22 , wherein said processor is to perform packed floating point operations during execution of said packed data instructions and to perform scalar floating point operations during execution of said scalar data instructions.  
     
     
         27 . The processor of  claim 22 , wherein said tag modifier unit is also to alter those tags of said plurality of tags that correspond to aliased registers to indicate empty sometime between execution of a most recent one of said packed data instructions to be executed prior to execution of a next one of said scalar data instructions and an attempted execution of said next one of said scalar data instructions to be executed since execution of said most recent one of said packed data instructions.  
     
     
         28 . The processor of  claim 22 , wherein said tag modifier unit is also to alter those tags of said plurality of tags that correspond to aliased registers to indicate empty in response to execution of a most recent one of said packed data instructions to be executed prior to execution of a next one of said scalar data instruction.  
     
     
         29 . The processor of  claim 22 , wherein said tag modifier unit is also to alter those tags of said plurality of tags that correspond to aliased registers to indicate empty responsive to an attempted execution of the first of said scalar data instructions to be executed since execution of a most recent one of said packed data instructions.  
     
     
         30 . A processor comprising: 
 a plurality of physical registers;    a memory unit to make said plurality of physical registers appear to software as a single software-visible register file that is used for saving scalar floating point data; and    a decode/execution unit to receive a packed data instruction that causes a packed data item to be written to a register in said single software-visible register file, wherein said packed data item is written in a mantissa field of said register and a value representing not a number or infinity is written in a sign and exponent field of said register.    
     
     
         31 . The processor of  claim 30 , wherein said floating point data includes both scalar and packed floating point data.  
     
     
         32 . A processor comprising: 
 a plurality of physical registers;    a decode unit to decode a first, second, third, and fourth type of instructions that each specify operations on different types of operands, said first, second and third types of instructions specifying the same software-visible registers that are aliased; and    a mapping unit, coupled to said decode unit and said plurality of physical registers, to map registers specified by instructions of the first type to registers in the plurality of registers in a stack referenced manner, and to map registers specified by instructions of the second, third, and fourth type to registers in the plurality of registers in a non-stack referenced manner.    
     
     
         33 . The processor of  claim 32 , wherein said first, second, third, and fourth types of instructions respectively specify operations on scalar floating point data, packed floating point data, packed integer data, and scalar integer data.  
     
     
         34 . The processor of  claim 32 , wherein said mapping unit includes a plurality of tags, each tag in said plurality of tags corresponding to a different one of said software-visible registers to identify if said register is in an empty state or a non-empty state.  
     
     
         35 . The processor of  claim 34 , wherein said mapping unit includes a tag modifier unit to alter each tag in said plurality of tags to indicate said empty state in response to said processor receiving one instruction.  
     
     
         36 . The processor of  claim 35 , wherein said first, second, third, and fourth types of instructions respectively specify operations on scalar floating point data, packed floating point data, packed integer data, and scalar integer data.  
     
     
         37 . The processor of  claim 34 , wherein said mapping unit includes a tag modifier unit to alter each tag in said plurality of tags to indicate said empty state responsive to execution of the most recent instruction of said second type to be executed prior to execution of a next instruction of said first type.  
     
     
         38 . The processor of  claim 34 , wherein said mapping unit includes a tag modifier unit to alter each tag in said plurality of tags to indicate said empty state in response to an attempted execution of the next instruction of said first type to be executed since execution of the most recent instruction of said second type.  
     
     
         39 . The process of  claim 34 , wherein said mapping unit includes a tag modifier unit to alter each tag of said plurality of tags to indicate said non-empty state sometime between execution of instructions of said first type and completion of execution of the next instruction of said third type to be executed.  
     
     
         40 . The processor of  claim 34 , wherein said mapping unit includes a tag modifier unit to alter each tag of said plurality of tags to indicate said non-empty state in response to executing the first instruction of said third type to be executed since executing instructions of said first type.  
     
     
         41 . The processor of  claim 40 , wherein said first, second, third, and fourth types of instructions respectively specify operations on scalar floating point data, packed floating point data, packed integer data, and scalar integer data.  
     
     
         42 . The processor of  claim 34 , wherein said mapping unit includes a tag modifier unit to alter each tag of said plurality of tags to indicate said non-empty state in response to executing every instruction of said third type.  
     
     
         43 . The processor of  claim 32 , wherein said mapping unit includes a top of stack field to identify one register in said same software-visible registers that are aliased as a current top of stack register, said mapping unit to alter said top of stack of stack field to an initialization value sometime between execution of instructions of said third type and completion of the next instruction of said first type to be executed.  
     
     
         44 . The process of  claim 32 , wherein each register of said same software-visible registers further comprises a sign and exponent field in which is to be written a value to indicate either not a number or infinity in response to execution of an instruction of said third instruction type that causes a result value to be written into that register.  
     
     
         45 . A processor comprising: 
 a plurality of physical registers;    a decode unit to decode a first, second, and third type of instruction that respectively specify operations on scalar floating point data, packed floating point data, and scalar integer data, said first and second types of instructions specifying the same software-visible registers that are aliased; and    a mapping unit, coupled to said decode unit and said plurality of physical registers, to map registers specified by instructions of the first, second and third types to registers in the plurality of registers in a non-stack referenced manner.    
     
     
         46 . The processor of  claim 45 , wherein said third type of instructions specify a different software-visible register file.