Magnetic random access memory

Abstract

TMR elements are arranged at the intersections between word lines and bit lines. One end of each word line is connected to the ground point through a row select switch. One end of each bit line is connected to a bit line bias circuit. In read operation, the bit line bias circuit applies a bias potential to all the bit lines. The selected word line is short-circuited to the ground point. Unselected word lines are set in a floating state.

1 - 100 . (Canceled).  
   
   
       101 . A magnetic random access memory comprising: 
 first interconnections;    second interconnections which cross said first interconnections;    a first cell array structure formed from first memory cells which are arranged between said first interconnections and said second interconnections to store data using a magnetoresistive effect;    third interconnections;    fourth interconnections which cross said third interconnections; and    a second cell array structure stacked on said first cell array structure and formed from second memory cells which are arranged between said third interconnections and said fourth interconnections to store data using a magnetoresistive effect.    
   
   
       102 . A memory according to  claim 101 , further comprising a bias circuit which applies a bias potential to all second interconnections electrically connected to a selected first interconnection when a read current is supplied between the selected first interconnection and a selected second interconnection.  
   
   
       103 . A memory according to  claim 101 , further comprising a bias circuit which applies a bias potential to all second interconnections electrically connected to a selected first interconnection when a read current is supplied between the selected first interconnection and selected second interconnections.  
   
   
       104 . A memory according to  claim 101 , further comprising a bias circuit which applies a bias potential to all fourth interconnections electrically connected to a selected third interconnection when a read current is supplied between the selected third interconnection and a selected fourth interconnection.  
   
   
       105 . A memory according to  claim 101 , further comprising a bias circuit which applies a bias potential to all fourth interconnections electrically connected to a selected third interconnection when a read current is supplied between the selected third interconnection and selected fourth interconnections.  
   
   
       106 . A memory according to  claim 101 , wherein one of said first interconnections and one of said third interconnections are connected in series or in parallel.  
   
   
       107 . A memory according to  claim 101 , wherein one of said second interconnections and one of said fourth interconnections are connected in series or in parallel.  
   
   
       108 . A magnetic random access memory comprising: 
 first interconnections;    second interconnections which cross said first interconnections;    first memory cells which are arranged between said first interconnections and said second interconnections to store data using a magnetoresistive effect;    third interconnections which cross said second interconnections; and    second memory cells which are arranged between said second interconnections and said third interconnections to store data using a magnetoresistive effect, wherein said first interconnections are arranged under said second interconnections, and said third interconnections are arranged above said second interconnections.    
   
   
       109 . A memory according to  claim 108 , wherein 
 said first interconnections and said third interconnections run in the same direction, and    said second interconnections run in a direction perpendicular to said first interconnections and said third interconnections.    
   
   
       110 . A memory according to  claim 108 , wherein said second interconnections are shared by said first memory cells and said second memory cells.  
   
   
       111 . A memory according to  claim 108 , further comprising a bias circuit which applies a bias potential to all second interconnections electrically connected to a selected first interconnection when a read current is supplied between the selected first interconnection and a selected second interconnection.  
   
   
       112 . A memory according to  claim 108 , further comprising a bias circuit which applies a bias potential to all second interconnections electrically connected to a selected first interconnection when a read current is supplied between the selected first interconnection and selected second interconnections.  
   
   
       113 . A memory according to  claim 108 , further comprising a bias circuit which applies a bias potential to all second interconnections electrically connected to a selected third interconnection when a read current is supplied between the selected third interconnection and a selected second interconnection.  
   
   
       114 . A memory according to  claim 108 , further comprising a bias circuit which applies a bias potential to all second interconnections electrically connected to a selected third interconnection when a read current is supplied between the selected third interconnection and selected second interconnections.  
   
   
       115 . A memory according to  claim 108 , further comprising a bias circuit which applies a bias potential to all first interconnections and all third interconnections electrically connected to a selected second interconnection when a read current is supplied between the selected second interconnection and a selected first interconnection.  
   
   
       116 . A memory according to  claim 108 , further comprising a bias circuit which applies a bias potential to all first interconnections and all third interconnections electrically connected to a selected second interconnection when a read current is supplied between the selected second interconnection and selected first interconnections.  
   
   
       117 . A memory according to  claim 108 , further comprising a bias circuit which applies a bias potential to all third interconnections and all first interconnections electrically connected to a selected second interconnection when a read current is supplied between the selected second interconnection and a selected third interconnection.  
   
   
       118 . A memory according to  claim 108 , further comprising a bias circuit which applies a bias potential to all third interconnections and all first interconnections electrically connected to a selected second interconnection when a read current is supplied between the selected second interconnection and selected third interconnections.  
   
   
       119 . A memory according to  claim 108 , wherein one of said first interconnections and one of said third interconnections are connected in series or in parallel.  
   
   
       120 - 135 . (Canceled).