Semiconductor memory device with magnetoresistance elements and method of writing data into the same

Abstract

A semiconductor memory device includes memory cells, first wirings, a first current driver circuit, and a second current driver circuit. The memory cell includes a magneto-resistive element having a first ferromagnetic film, an insulating film formed on the first ferromagnetic film, and a second ferromagnetic film formed on the insulating film. The first wiring is provided in close proximity to and insulated from the magneto-resistive element. The first current driver circuit supplies a first current to the first wiring in a write operation to produce a magnetic field around the magneto-resistive elements. The second current driver circuit supplies a second current between the first and second ferromagnetic films via the insulating film in a write and a read operation.

1 . A semiconductor memory device comprising: 
 memory cells each of which includes a magneto-resistive element having a first ferromagnetic film, an insulating film formed on the first ferromagnetic film, and a second ferromagnetic film formed on the insulating film;    first wirings each of which is provided in close proximity to and insulated from the magneto-resistive element;    a first current driver circuit which supplies a first current to the first wiring in a write operation to produce a magnetic field around the magneto-resistive elements; and    a second current driver circuit which supplies a second current between the first and second ferro-magnetic films via the insulating film in a write and a read operation.    
   
   
       2 . The semiconductor memory device according to  claim 1 , wherein the second current is equal to or less than ⅓ of the first current.  
   
   
       3 . The semiconductor memory device according to  claim 1 , wherein the first current driver circuit, at the end of a write operation, stops supplying the first current after the second current driver circuit stops supplying the second current.  
   
   
       4 . The semiconductor memory device according to  claim 1 , wherein the second current driver circuit, when supplying the second current, sets one of the first and second ferromagnetic films which functions as a free layer to a higher potential than the potential of the other ferromagnetic film functioning as a pinning layer.  
   
   
       5 . The semiconductor memory device according to  claim 1 , wherein each of the memory cells further includes a switching transistor having a gate and a current path one end of which is connected to one of the first and second ferromagnetic films and the other end of which is connected to a first potential node, 
 the second current driver circuit includes a first current source and a voltage source,    in the write operation, the first current source supplies the second current from the other of the first and second ferromagnetic films, and in the write operation, the voltage source supplies a voltage to the gate of the switching transistor.    
   
   
       6 . The semiconductor memory device according to  claim 5 , further comprising: 
 a memory cell array in which the memory cells are arranged in a matrix;    write word lines which connect, in common, the first wirings provided in the proximity of the magneto-resistive elements of the memory cells in a same row;    select word lines which connect, in common, the gates of the switching transistors of the memory cells in a same row;    bit lines which connect, in common, the other of the first and second ferromagnetic films of each of the memory cells in a same column;    a row decoder which selects the write word line and select word line; and    a column decoder which selects the bit line, wherein    the first current driver circuit supplies the first current to the write word line selected by the row decoder,    the first current source supplies the second current to the bit line selected by the column decoder; and    the second voltage source supplies the voltage to the select word line selected by the row decoder.    
   
   
       7 . The semiconductor memory device according to  claim 6 , further comprising: 
 a first withdrawing wiring and a first contact plug which connect one of the first and second ferromagnetic films and one end of the current path of the switching transistor; and    a second withdrawing wiring and a second contact plug which connect the other of the first and second ferromagnetic films and the bit line, wherein    the first and second contact plugs are formed in regions other than the regions right above and under the magneto-resistive elements.    
   
   
       8 . The semiconductor memory device according to  claim 6 , wherein the memory cell includes: 
 the switching transistor which includes a source and a drain region formed so as to be isolated from each other at the surface of a semiconductor substrate, and a gate electrode formed on the semiconductor substrate with a gate insulating film interposed therebetween, and which is covered with a first interlayer insulating film formed on the semiconductor substrate;    a withdrawing wiring formed on the first interlayer insulating film;    a first contact plug which is formed in the first interlayer insulating film and connects the drain region of the switching transistor and the withdrawing wiring;    the magneto-resistive element formed on the withdrawing wiring; and    the first wiring which is formed in a region right under the magneto-resistive element in the first interlayer insulating film and which is made of a metal wiring layer located at the lowest layer in the first interlayer insulating film.    
   
   
       9 . The semiconductor memory device according to  claim 8 , further comprising: 
 a second contact plug which is formed in the first interlayer insulating film and connects, in common, the source regions of the switching transistors included in the memory cells.    
   
   
       10 . The semiconductor memory device according to  claim 6 , wherein the first current source includes a second and a third current source arranged so as to face each other via the memory cell array along the bit line, 
 the second current source supplies the second current to the bit lines in even-numbered columns, and    the third current source supplies the second current to the bit lines in odd-numbered columns.    
   
   
       11 . The semiconductor memory device according to  claim 1 , further comprising: 
 a memory cell array in which the memory cells are arranged in a matrix;    write word lines which connect, in common, the first wirings provided in the proximity of the magneto-resistive elements of the memory cells in a same row;    select word lines which connect, in common, one of the first and second ferromagnetic films of each of the memory cells in a same row;    bit lines which connect, in common, the other of the first and second ferromagnetic films of each of the memory cells in a same column;    a row decoder which selects the write word line and select word line; and    a column decoder which selects the bit line, wherein    the first current driver circuit supplies the first current to the write word line selected by the row decoder, and    the second current driver circuit includes a first current source and a current sink,    one of the first current source and the current sink is connected to the bit line selected by the column decoder and the other of the first current source, and    the current sink is connected to the select word line selected by the row decoder.    
   
   
       12 . The semiconductor memory device according to  claim 11 , further comprising: 
 a first withdrawing wiring and a first contact plug which connect one of the first and second ferromagnetic films and the select word line; and    a second withdrawing wiring and a second contact plug which connect the other of the first and second ferromagnetic films and the bit line, wherein    the first and second contact plugs are formed in regions other than the regions right above and under the magneto-resistive elements.    
   
   
       13 . The semiconductor memory device according to  claim 11 , wherein the first current source includes a second and a third current source arranged so as to face each other via the memory cell array along the bit line, 
 the second current source is connected to either the bit lines in even-numbered columns or the select word lines in even-numbered rows, and    the third current source is connected to the bit lines in odd-numbered columns when the second current source is connected to the bit lines in the even-numbered columns and is connected to the select word lines in odd-numbered rows when the second current source is connected to the select word lines in the even-numbered rows.    
   
   
       14 . The semiconductor memory device according to  claim 1 , further comprising: 
 a memory cell array in which the memory cells are arranged in a matrix;    write bit lines which connect, in common, the first wiring provided in the proximity of the magneto-resistive elements of the memory cells in a same column;    select bit lines which connect, in common, one of the first and second ferromagnetic films of each of the memory cells in a same column;    word lines which connect, in common, the other of the first and second ferromagnetic films of each of the memory cells in a same row;    a row decoder which selects the word line; and    a column decoder which selects the write bit line and the select bit line, wherein    the first current driver circuit supplies the first current to the write bit line selected by the column decoder, and    the second current driver circuit includes a first current source and a current sink,    one of the first current source and the current sink is connected to the word line selected by the row decoder, and    the other of the first current source and the current sink is connected to the select bit line selected by the column decoder.    
   
   
       15 . The semiconductor memory device according to  claim 14 , further comprising: 
 a first withdrawing wiring and a first contact plug which connect one of the first and second ferromagnetic films and the select bit line; and    a second withdrawing wiring and a second contact plug which connect the other of the first and second ferromagnetic films and the word line, wherein    the first and second contact plugs are formed in regions other than the regions right above and under the magneto-resistive elements.    
   
   
       16 . The semiconductor memory device according to  claim 14 , wherein the first current source includes a second and a third current source arranged so as to face each other via the memory cell array along the bit line, 
 the second current source is connected to either the word lines in even-numbered rows or the select bit lines in even-numbered columns, and    the third current source is connected to the word lines in odd-numbered rows when the second current source is connected to the word lines in the even-numbered rows and is connected to the select bit lines in odd-numbered columns when the second current source is connected to the select bit lines in the even-numbered columns.    
   
   
       17 . The semiconductor memory device according to  claim 1 , further comprising: 
 a withdrawing wiring formed so as to make contact with one of the first and second ferromagnetic films, wherein    the second current driver circuit, when supplying the second current, sets one of the first and second ferromagnetic films at a higher potential than the potential of the other.    
   
   
       18 . The semiconductor memory device according to  claim 1 , further comprising: 
 a second interlayer insulating film formed so as to cover the memory cells; and    a thermal conduction preventing region which is formed between the magneto-resistive elements of the memory cells adjacent to one another in the second interlayer insulating film and which has thermal conductivity lower than that of the second interlayer insulating film.    
   
   
       19 . The semiconductor memory device according to  claim 18 , wherein the thermal conduction preventing region is a cavity made in the second interlayer insulating film.  
   
   
       20 . The semiconductor memory device according to  claim 1 , further comprising a stress applying layer formed so as to face the insulating film, with one of the first and second ferromagnetic films which functions as a free layer between the stress applying layer and the insulating film, wherein 
 the free layer has a positive magnetostriction constant and a larger thermal expansion coefficient than that of the stress applying layer.    
   
   
       21 . The semiconductor memory device according to  claim 20 , wherein the absolute value of the magnetostriction constant is larger than 5×10 −6 .  
   
   
       22 . The semiconductor memory device according to  claim 20 , wherein the stress applying layer functions as a part of the free layer.  
   
   
       23 . The semiconductor memory device according to  claim 1 , further comprising a stress applying layer formed so as to face the insulating film, with one of the first and second ferromagnetic films which functions as a free layer between the stress applying layer and the insulating film, wherein 
 the free layer has a negative magnetostriction constant and a larger thermal expansion coefficient than that of the stress applying layer.    
   
   
       24 . The semiconductor memory device according to  claim 23 , wherein the absolute value of the magnetostriction constant is larger than 5×10 −6 .  
   
   
       25 . The semiconductor memory device according to  claim 23 , wherein the stress applying layer functions as a part of the free layer.  
   
   
       26 . The semiconductor memory device according to  claim 1 , wherein one of the first and second ferro-magnetic films which functions as a free layer has its thermal expansion coefficient varied so as to decrease from the interface with the insulating film along the film thickness.  
   
   
       27 . The semiconductor memory device according to  claim 26 , wherein the free layer is formed of an alloy which includes Ni and Fe and has its Ni content varied so as to decrease from the interface with the insulating film along the film thickness.  
   
   
       28 . The semiconductor memory device according to  claim 1 , further comprising a piezoelectric effect film formed so as to face the insulating film, with one of the first and second ferromagnetic films which functions as a free layer between the piezoelectric effect film and the insulating film.  
   
   
       29 . A method of writing data into a semiconductor memory device including memory cells arranged in matrix, the memory cell having a magneto-resistive element which includes a first ferromagnetic film, an insulating film formed on the first ferromagnetic film, and a second ferromagnetic film formed on the insulating film, the method comprising: 
 causing a first current to flow, via the insulating film, between the first and second ferromagnetic films of the magneto-resistive element included in a first selected memory cell;    applying a magnetic field to the magneto-resistive element by causing a second current to flow in a wiring provided in the vicinity of the magneto-resistive element, with the first current flowing in the magneto-resistive element of the first selected memory cell;    stopping the supply of the first current; and    stopping the supply of the second current after the supply of the first current is stopped.    
   
   
       30 . The method according to  claim 29 , wherein 
 the first current is supplied to the magneto-resistive elements included in the first selected memory cells which are arranged in a same row and into which first data is to be written,    the second current is supplied so as to flow from one end of the wiring to the other end, and    the method further comprises: 
 causing a third current to flow, via the insulating film, between the first and second ferromagnetic films of the magneto-resistive elements of second selected memory cells which are arranged in the same row as the first selected memory cells and into which second data is to be written, after the supply of the second current is stopped;  
 applying a magnetic field to the magneto-resistive element by causing a fourth current to flow in the wiring provided in the vicinity of the magneto-resistive element from the other end of the wiring toward the one end, with the third current flowing in the magneto-resistive elements in the second selected memory cells;  
 stopping the supply of the third current; and  
 stopping the supply of the fourth current after the supply of the third current is stopped.