Semiconductor integrated circuit device

Abstract

A semiconductor integrated circuit device is provided, in which variation in the threshold voltage of a MISFET, for example, a MISFET pair that constitute a sense amplifier, can be reduced. In a logic circuit area over which a logic circuit such as a sense amplifier circuit required to drive a memory cell is formed, n-type active areas having no gate electrode are arranged at both edges of active areas over which a p-channel MISFET pair for constituting a sense amplifier are formed. Assuming that the width between active areas nwp 1 and nw 1 is L 4, the width between active areas nwp 2 and nw 2 is L 6, and the width between active areas nwp 1 and nwp 2 is L 5, (L 4 -L 5 ), (L 6 -L 5 ), and (L 4 -L 6 ) are set equal to almost zero or smaller than twice the minimum processing dimension, so that the variation in shape of the device isolation trenches with the widths L 4, L 5, and L 6 can be reduced, and the threshold voltage difference in the MISFET pair can be reduced.

1 - 17 . (Cancelled)  
   
   
       18 . A semiconductor integrated circuit device, comprising: 
 (a) a first device forming area on which an n-channel MISFET pair in which a gate electrode and a source-drain area thereof are cross-connected are formed, and a second device forming area on which a p-channel MISFET pair in which a gate electrode and a source-drain area thereof are cross-connected are formed;    (b) first and second isolation areas adjacent to both edges of the first device forming area, the first and second isolation areas being formed in first and second device isolation trenches, respectively, and third and fourth isolation areas adjacent to both edges of the second device forming area, the third and fourth isolation areas being formed in third and fourth device isolation trenches, respectively;    (c) first and second gate electrodes of the n-channel MISFET pair, the first gate electrode being arranged over the first device forming area and the first isolation area, and the second gate electrode being arranged over the first device forming area and the second isolation area; and    (d) third and fourth gate electrodes of the p-channel MISFET pair, the third gate electrode being arranged over the second device forming area and the third isolation area, and the fourth gate electrode being arranged over the second device forming area and the fourth isolation area;    (e) wherein width difference between the first and second device isolation trenches and width difference between the third and fourth device isolation trenches are smaller than twice the minimum processing dimension.    
   
   
       19 . The semiconductor integrated circuit device according to  claim 18 , 
 wherein the widths of the first and second device isolation trenches are larger than those of the third and fourth device isolation trenches.    
   
   
       20 . A semiconductor integrated circuit device, comprising: 
 (a) first and second memory cell forming areas; and    (b) a plurality of active areas arranged between the first and second memory cell forming areas, the active areas being comprised of a plurality of p-type active areas and at least two n-type active areas;    wherein the n-type active areas are arranged over both edges of the plurality of active areas.    
   
   
       21 . The semiconductor integrated circuit device according to  claim 20 , 
 wherein, over the n-type active area, a p-channel MISFET pair in which a gate electrode and a source-drain area thereof are cross-connected is formed.    
   
   
       22 . The semiconductor integrated circuit device according to  claim 20 , 
 wherein the first and second isolation areas are located over both edges of the n-type active area, the first and second isolation areas being formed in first and second device isolation trenches, respectively; and width difference between the first and second device isolation trenches is smaller than twice the minimum processing dimension.    
   
   
       23 . A semiconductor integrated circuit device, comprising: 
 (a) a device forming area; and    (b) a pair of MISFET formed over the device forming area on which a gate electrode and a source-drain area thereof are cross-connected,    wherein a portion of the gate electrode of the MISFET is provided over the device forming area, the portion not functioning to isolate the source and drain of the MISFET.    
   
   
       24 . A semiconductor integrated circuit device, comprising: 
 (a) a device forming area; and    (b) a pair of MISFET formed over the device forming area on which a gate electrode and a source-drain area thereof are cross-connected,    wherein the gate electrode of the MISFET includes a portion under which no channel is formed.    
   
   
       25 . The semiconductor integrated circuit device according to  claim 24 , 
 wherein the gate electrode includes a portion arranged so as to surround a part of the device forming area and a lead-out portion extending from the portion.    
   
   
       26 . A semiconductor integrated circuit device, comprising: 
 a MISFET pair which is arranged so that gate electrodes thereof reach edges of a device active area and is formed so that a source area and a drain area are isolated in the device active area,    wherein device isolation trenches with same width are adjacently arranged at both sides of the device active area over which the MISFET pair is arranged.    
   
   
       27 . A semiconductor integrated circuit device, comprising: 
 a p-channel MISFET pair which is arranged so that gate electrodes thereof reach edges of a device active area and is formed so that a source area and a drain area are isolated in the device active area,    wherein p-channel MISFET device isolation area with same width are adjacently arranged at both sides of the device active area over which the p-channel MISFET pair is arranged.