Embedded DRAM cache

Abstract

A large level three (L3) cache is integrated within the system chipset. The L3 cache is comprised of multiple embedded memory cache arrays. Each array is accessible independently of each other, providing parallel access to the L3 cache. By placing the L3 cache within the chipset, it is closer to the system processor with respect to the system memory. By using independent arrays, the L3 cache can handle numerous simultaneous requests. This reduces average memory latency and thus, increases system bandwidth and overall performance. By using embedded memory, the L3 cache can be implemented on the chipset and be much larger than the L1 and L2 caches without substantially increasing the size of the chipset and system.

1 - 28 . (cancelled)  
   
   
       29 . An integrated circuit for use with a processor system, said integrated circuit comprising: 
 a memory controller for controlling a system memory of the processor system;    a processor interface coupled to said memory controller, said processor interface for transmitting information between a processor and the system memory;    a cache memory coupled to said memory controller and said processor interface, said cache memory comprising a plurality of independently accessible memory arrays; and    a master scheduler coupled to each of said memory arrays, said master scheduler for processing requests for information from the processor and other components by independently and concurrently forwarding information, and resolving conflicts for information, between said memory arrays, said processor, and said other components.    
   
   
       30 . The integrated circuit of  claim 29 , wherein each one of said memory arrays comprises embedded memory.  
   
   
       31 . The integrated circuit of  claim 29 , wherein said integrated circuit include eight memory arrays.  
   
   
       32 . The integrated circuit of  claim 29 , wherein said memory arrays are operated to as a direct mapped cache memory.  
   
   
       33 . The integrated circuit of  claim 29 , wherein said cache memory forms a lower level cache memory system in combination with at least one off-chip higher level cache memory.  
   
   
       34 . The integrated circuit of  claim 33 , wherein said cache memory forms a third level cache memory of a cache memory system comprising a first level cache memory and a second level cache memory of a processor coupled to said integrated circuit.  
   
   
       35 . A multi-port bus bridge, formed on an integrated circuit, the bus bridge comprising: 
 a communication network;    a cache memory, coupled to said communication network, said cache memory comprising a plurality of independently and concurrently accessible units, each of said units comprising an embedded unit memory and a unit memory controller;    a plurality of ports, for communicating with respective off-chip devices;    a plurality of port controllers, each associated with a respective one of said plurality of ports, each of said port controllers coupled to said communication network and for transmitting information among said plurality of ports and said cache memory;    a bridge controller, coupled to said plurality of port controllers and said cache memory, said bridge controller processing requests received over said plurality of ports to resolve conflicts between said units to permit information to be concurrently and independently forwarded between said port controllers and said units.    
   
   
       36 . The multi-port bridge of  claim 35 , wherein cache memory is a direct mapped cache.  
   
   
       37 . The multi-port bridge of  claim 35 , wherein each said embedded unit memory comprises a tag array and a cache storage array.  
   
   
       38 . The multi-port bridge of  claim 35 , wherein said plurality of ports comprise: 
 a processor port, for coupling to a processor of a processor based system;    a memory port, for coupling to a system memory of said processor based system; and    an expansion bus port, for coupling to an expansion bus of said processor based system.    
   
   
       39 . The multi-port bridge of  claim 35 , wherein multi-port bridge is a north bridge of a computer system.  
   
   
       40 . The multi-port bridge of  claim 38 , wherein said cache memory is one of a plurality of cache memories in a cache memory system of said processor based system.