Method to chemically remove metal impurities from polycide gate sidewalls

Abstract

An embodiment includes a process of forming a gate stack that acts to resist the redeposition to the semiconductive substrate of mobilized metal such as from a metal gate electrode. An embodiment also relates to a system that achieves the process. An embodiment also relates to a gate stack structure that provides a composition that resists the redeposition of metal during processing and field use.

1 . A system comprising: 
 a semiconductor structure comprising a substrate;    a metal film disposed over the substrate;    wherein the metal film is selected from Al, Cu, Ag, Au, Ti, Zr, Hf, Ni, Co, Pd, Pt, V, Ta, Nb, Cr, Mo, W, Sc, Yt, La, Ce, Rh, Os, Ir, and combinations thereof;    a processing tool comprising a chamber; and    at least one getterer composition selected from a getterer gas and a getterer solid, wherein the at least one getterer composition comprises a thermodynamic or kinetic advantage over the semiconductor structure for combining with the metal film.    
   
   
       2 . The system according to  claim 1 , wherein the getterer solid comprises a dielectric layer disposed over the semiconductor structure.  
   
   
       3 . The system according to  claim 1 , wherein the getterer solid comprises a metal film disposed over the semiconductor structure.  
   
   
       4 . The system according to  claim 1 , wherein the getterer solid comprises a dielectric layer or metal film disposed over the semiconductor structure, wherein the dielectric layer or metal film comprises from about 1% fluorine to about 30% fluorine.  
   
   
       5 . The system according to  claim 1 , wherein the getterer solid comprises a conductive nitride layer disposed over the semiconductor structure, wherein the conductive nitride layer comprises from about 0.1% fluorine to about 30% fluorine.  
   
   
       6 . The system according to  claim 1 , wherein the getterer gas comprises a fluorine-containing composition.  
   
   
       7 . The system according to  claim 1 , wherein the getterer gas comprises a fluorine-containing composition in a volumetric concentration range from about 0.1% to about 10%.  
   
   
       8 . The system according to  claim 1 , wherein the getterer gas comprises NF 3  in a volumetric concentration range from about 0.1% to about 10%.  
   
   
       9 . The system according to  claim 1 , wherein the getterer gas comprises a halogen selected from F, Cl, Br, I, and combinations thereof.  
   
   
       10 . A system comprising: 
 a gate dielectric layer disposed over a semiconductor substrate;    a doped polysilicon electrode disposed over the gate dielectric layer;    a tungsten nitride barrier layer disposed over the polysilicon electrode;    a metal film disposed over the tungsten nitride barrier layer, wherein the metal film is selected from Al, Cu, Ag, Au, Ti, Zr, Hf, Ni, Co, Pd, Pt, V, Ta, Nb, Cr, Mo, W, Sc, Yt, La, Ce, Rh, Os, Ir, and combinations thereof;    a processing tool comprising at least one chamber; and    at least one composition selected from a gas and a solid, wherein the at least one composition comprises a thermodynamic or kinetic advantage over the semiconductor substrate for combining with metal from the metal film.    
   
   
       11 . The system according to  claim 10 , wherein the solid comprises a dielectric film disposed over the metal electrode.  
   
   
       12 . The system according to  claim 10 , wherein the solid comprises a dielectric film disposed over the semiconductor structure, wherein the dielectric film comprises from about 0.1% fluorine to about 30% fluorine.  
   
   
       13 . The system according to  claim 10 , wherein the solid comprises a nitride dielectric film disposed over the semiconductor structure, wherein the nitride dielectric film comprises from about 0.1% fluorine to about 30% fluorine.  
   
   
       14 . The system according to  claim 10 , wherein the gas comprises a fluorine-containing composition.  
   
   
       15 . The system according to  claim 10 , wherein the gas comprises a fluorine-containing composition in a volumetric concentration range from about 0.1% to about 10%.  
   
   
       16 . The system according to  claim 10 , wherein the gas comprises NF 3  in a volumetric concentration range from about 0.1% to about 10%.  
   
   
       17 . The system according to  claim 10 , wherein the solid comprises a nitride dielectric film disposed over the semiconductor structure, wherein the nitride dielectric film comprises from about 0.1% fluorine to about 30% fluorine; and 
 wherein the gas comprises NF 3  in a concentration range from about 0.1% to about 10%.    
   
   
       18 . A gate stack comprising: 
 a substrate;    a gate dielectric layer disposed above and on the substrate;    a doped polysilicon layer disposed over the gate dielectric layer;    a conductive barrier layer disposed over the polysilicon layer;    a metal film disposed over the conductive barrier layer;    a dielectric cap layer disposed over the metal film; and    wherein at least one of the conductive barrier layer, the metal film, and the dielectric cap layer include a halogen disposed therein in a range from about 0.1% to about 30%.    
   
   
       19 . The gate stack according to  claim 18 , wherein the halogen includes fluorine.  
   
   
       20 . The gate stack according to  claim 18 , wherein the conductive barrier layer, the metal film, and the dielectric cap layer each include a halogen disposed therein in a range from about 0.1% to about 30%.  
   
   
       21 . The gate stack according to  claim 20 , wherein the halogen includes fluorine.  
   
   
       22 . The gate stack according to  claim 18 , wherein for the conductive barrier layer, the metal film, and the dielectric cap layer only two thereof include a halogen disposed therein in a range from about 0.1% to about 30%.  
   
   
       23 . The gate stack according to  claim 22 , wherein the halogen includes fluorine.  
   
   
       24 . The gate stack according to  claim 18 , wherein for the conductive barrier layer, the metal film, and the dielectric cap layer only one thereof comprises a halogen disposed therein in a range from about 0.1% to about 30%.  
   
   
       25 . The gate stack according to  claim 24 , wherein the halogen comprises fluorine.  
   
   
       26 . A computer system, comprising: 
 a processor;    a memory system coupled to the processor;    an input/output (I/O) circuit coupled to the processor and the memory system; and    a gate stack disposed in at least one of the processor and the I/O circuit, the gate stack including: 
 a substrate;  
 a gate dielectric layer disposed above and on the substrate;  
 a doped polysilicon layer disposed over the gate dielectric layer;  
 a conductive barrier layer disposed over the polysilicon layer;  
 a metal film disposed over the conductive barrier layer;  
 a dielectric cap layer disposed over the metal film; and  
 wherein at least one of the conductive barrier layer, the metal film, and the dielectric cap layer include a halogen disposed therein in a range from about 0.1% to about 30%.  
   
   
   
       27 . The computer system according to  claim 26 , wherein the processor is disposed in a host selected from a clock, a television, a cell phone, a personal computer, an automobile, an industrial control system, and an aircraft.  
   
   
       28 . A system, comprising: 
 a circuit module having a chip set; and    a gate stack disposed in at least one of the chips in the chip set, the gate stack including: 
 a substrate;  
   a gate dielectric layer disposed above and on the substrate; 
 a doped polysilicon layer disposed over the gate dielectric layer;  
 a conductive barrier layer disposed over the polysilicon layer;  
 a metal film disposed over the conductive barrier layer;  
 a dielectric cap layer disposed over the metal film; and  
 wherein at least one of the conductive barrier layer, the metal film, and the dielectric cap layer include a halogen disposed therein in a range from about 0.1% to about 30%.  
   
   
   
       29 . The system according to  claim 28 , wherein the circuit module is disposed in a host selected from a memory module, a device driver, a power module, a communication modem, a processor module, and an application specific integrated circuit.  
   
   
       30 . An semiconductor device, comprising: 
 a semiconductor substrate having a first conductivity type, including at least two diffused regions having a second conductivity type;    a gate dielectric layer disposed between the at least two diffused regions;    a polysilicon layer disposed over the gate dielectric;    an electrically conductive diffusion barrier layer disposed over the polysilicon layer;    a metal layer disposed over the diffusion barrier layer; and    at least one of the gate dielectric, polysilicon, diffusion barrier and metal layer comprises a halogen from at least 0.1% to less than 30% by weight of the layer.    
   
   
       31 . The semiconductor device of  claim 30  further comprising a cap dielectric layer disposed over the metal layer.  
   
   
       32 . The semiconductor device of  claim 31  further comprising etching the cap dielectric, metal, diffusion barrier, polysilicon layers to form a gate stack disposed between the at least two diffused regions.  
   
   
       33 . The semiconductor device of  claim 32  further comprising a sidewall spacer dielectric layer disposed over sidewalls of the gate stack.  
   
   
       34 . The semiconductor device of  claim 33  further comprising at least one of the cap dielectric and the sidewall spacer comprises a halogen from at least 0.1% to less than 30% by weight of the layer.  
   
   
       35 . The semiconductor device of  claim 34  further comprising the gate dielectric including silicon dioxide.  
   
   
       36 . The semiconductor device of  claim 34  further comprising the polysilicon layer doped with an N type dopant.  
   
   
       37 . The semiconductor device of  claim 34  further comprising the electrically conductive diffusion barrier layer including at least one material selected from the list including tungsten (W), titanium (Ti), nickel (Ni) and chrome (Cr), or combinations thereof.  
   
   
       38 . The semiconductor device of  claim 34  further comprising the electrically conductive diffusion barrier layer including a metal nitride.  
   
   
       39 . The semiconductor device of  claim 38  further comprising the metal nitride selected from the list including tungsten nitride and titanium nitride.  
   
   
       40 . The semiconductor device of  claim 34  further comprising the metal layer including at least one material selected from the list including Al, Cu, Ag, Au, Ti, Zr, Hf, Ni, Co, Pd, Pt, V, Ta, Nb, Cr, Mo, W, Sc, Yt, La, Ce, Rh, Os, Ir, and combinations thereof.  
   
   
       41 . The semiconductor device of  claim 34  further comprising the cap dielectric including silicon oxides and silicon nitrides.  
   
   
       42 . The semiconductor device of  claim 34  further comprising the sidewall spacer including silicon oxides and silicon nitrides.  
   
   
       43 . The semiconductor device of  claim 34  further comprising the halogen including fluorine.