Semiconductor element and process for manufacturing the same

Abstract

A semiconductor quantum memory element is disclosed which can share the terminals easily among a plurality of memory elements and can pass a high current and which is strong against noises. In order to accomplish this a control electrode is formed so as to cover the entirety of thin film regions connecting low-resistance regions. As a result, the element can have a small size and can store information with high density. Thus, a highly integrated, low power consumption non-volatile memory device can be realized with reduced size. A method of forming a memory element is also disclosed including performing the following steps of forming a first insulating layer, a second insulating layer, a first conductive layer and a layer of amorphous silicon. The amorphous silicon layer is crystallized to a polycrystalline silicon film. Semiconductor drains are deposited to form charge trapping and storage regions. A fourth insulating layer is deposited over the drains and a second conductive layer is deposited over a layer of silicon dioxide to form a control electrode of the memory element.

1 - 36 . (Canceled)  
   
   
       37 . A semiconductor memory device comprising: 
 a plurality of memory cells including a first memory cell, a second memory cell, a third memory cell, and a fourth memory cell;    each of the plurality of memory cells comprising a first low-resistance region and a second low-resistance region, a semiconductor current path connected between the first and second low-resistance regions, a plurality of small charge storage nodes surrounded by an insulator which acts as a potential barrier for the charge storage nodes, wherein the charge storage node is located between a control electrode and the current path;    wherein the first low-resistance region of the first memory cell is connected to the first low-resistance region of the second memory cell,    wherein the first low-resistance region of the third memory cell is connected to the first low-resistance region of the fourth memory cell,    wherein a control electrode of the first memory cell is connected to a control electrode of the third memory cell, and    wherein a control electrode of the second memory cell is connected to a control electrode of the fourth memory cell.    
   
   
       38 . A semiconductor memory device according to  claim 37 , 
 wherein the current path between the first and second low-resistance region of the first memory cell is extended in a first direction, and    wherein a line connected between the control electrode of the first memory cell and the control electrode of the third memory cell is extended in the first direction.    
   
   
       39 . A semiconductor memory device according to  claim 37 , 
 wherein the current path between the first and second low-resistance region of the first memory cell is extended in a first direction, and    wherein a line connected between the control electrode of the first memory cell and the control electrode of the third memory cell is extended in a second direction crossing the first direction.    
   
   
       40 . A semiconductor memory device according to  claim 37 , 
 wherein the current path of each of the plurality of memory cells is located on an insulator.    
   
   
       41 . A semiconductor memory device according to  claim 37 , 
 wherein each of the plurality of memory cells stores information by a difference of an electron charge stored in each of the charge storage nodes.    
   
   
       42 . A semiconductor memory device according to  claim 41 , 
 wherein a threshold voltage varies within a relatively small range when a relatively small voltage is applied between the first and second low-resistance region, and a threshold voltage varies within a relatively large range when a relatively large voltage is applied between the first and second low-resistance region.    
   
   
       43 . A semiconductor memory device according to  claim 37 , 
 wherein each of the plurality of memory cells further includes a thin film region connected between the first and second low-resistance region, the current path being formed in the thin film region, and    wherein the thin film region of each of the plurality of memory cells is covered with the control electrode of each of the plurality of memory cells.    
   
   
       44 . A semiconductor memory device comprising: 
 a plurality of memory cells including a first memory cell, a second memory cell, a third memory cell, and a fourth memory cell;    each of the plurality of memory cells comprising a first low-resistance region and a second low-resistance region, a semiconductor current path connected between the first and second low-resistance regions, a plurality of small charge storage nodes surrounded by an insulator which acts as a potential barrier for the charge storage nodes, wherein the charge storage node is located between a control electrode and the current path,    wherein the semiconductor memory device supplies a difference potential more than 1V between the first and second low-resistance region of a read operation.    
   
   
       45 . A semiconductor memory device according to  claim 44 , 
 wherein the current path of each of the plurality of memory cells is located on an insulator.    
   
   
       46 . A semiconductor memory device according to  claim 44 , 
 wherein each of the plurality of memory cells stores information by a difference of an electron charge stored in each charge storage node.    
   
   
       47 . A semiconductor memory device according to  claim 46 , 
 wherein a threshold voltage varies within a relatively small range when a relatively small voltage is applied between the first and second low-resistance region, and a threshold voltage varies within a relatively large range when a relatively large voltage is applied between the first and second low-resistance region.    
   
   
       48 . A semiconductor memory device according to  claim 44 , 
 wherein each of the plurality of memory cells further includes a thin film region connected between the first and second low-resistance region, the current path being formed in the thin film region, and    wherein the thin film region of each of the plurality of memory cells is covered with the control electrode of each of the plurality of memory cells.