Gettering using voids formed by surface transformation

Abstract

One aspect of this disclosure relates to a method for creating a gettering site in a semiconductor wafer. In various embodiments, a predetermined arrangement of a plurality of holes is formed in the semiconductor wafer through a surface of the wafer. The wafer is annealed such that the wafer undergoes a surface transformation to transform the arrangement of the plurality of holes into a predetermined arrangement of at least one empty space of a predetermined size within the wafer to form the gettering site. One aspect relates to a semiconductor wafer. In various embodiments, the wafer includes at least one device region, and at least one gettering region located proximate to the at least one device region. The gettering region includes a precisely-determined arrangement of a plurality of precisely-formed voids that are formed within the wafer using a surface transformation process. Other aspects and embodiments are provided herein.

1 . A semiconductor wafer, comprising: 
 at least one device region; and    at least one gettering region located proximate to the at least one device region, the at least one gettering region including a precisely-determined arrangement of a plurality of precisely-formed voids formed within the wafer using a surface transformation process.    
   
   
       2 . The wafer of  claim 1 , wherein the at least one gettering region includes one gettering region to getter the entire wafer.  
   
   
       3 . The wafer of  claim 1 , wherein the at least one gettering region includes a plurality of gettering regions positioned under a plurality of device regions.  
   
   
       4 . The wafer of  claim 1 , wherein the precisely-determined arrangement of a plurality of voids is uniformly distributed through the at least one gettering region.  
   
   
       5 . The wafer of  claim 1 , wherein the plurality of voids are separated by a critical length (λ C ) that is dependent on a radius (R C ) of a number of holes used to form the plurality of voids using a surface transformation process.  
   
   
       6 . The wafer of  claim 1 , wherein each of the voids has an interior surface that includes dangling bonds such that the plurality of voids getter impurities from the at least one device region.  
   
   
       7 . The wafer of  claim 6 , wherein: 
 the at least one gettering region has a volume; and    the precisely-determined arrangement of the plurality of precisely-formed voids is formed to provide a large ratio between the interior surface of the plurality of precisely-formed voids and the volume to enhance gettering.    
   
   
       8 . The wafer of  claim 1 , wherein the plurality of precisely-formed voids includes a sphere-shaped void.  
   
   
       9 . The wafer of  claim 1 , wherein the plurality of precisely-formed voids includes a pipe-shaped void.  
   
   
       10 . The wafer of  claim 1 , wherein the plurality of precisely-formed voids includes a plate-shaped void.  
   
   
       11 . The wafer of  claim 1 , wherein the at least one device region includes a plurality of device regions and the at least one gettering region includes a plurality of gettering regions.  
   
   
       12 . The wafer of  claim 1 , wherein the at least one device region extends across a majority of a wafer area.  
   
   
       13 . A semiconductor structure, comprising: 
 a gettering region proximate to a device region in a semiconductor wafer;    the gettering region including a precisely-determined arrangement of a plurality of precisely-formed voids through a surface transformation process, each of the voids having an interior surface that includes dangling bonds such that the plurality of voids getter impurities from the at least one device region;    a transistor formed using the device region, the transistor including 
 a gate dielectric over the device region;  
 a gate over the gate dielectric; and  
 a first diffusion region and a second diffusion region formed in the 
 device region, the first and second diffusion regions being separated by a channel region formed in the device region between the gate and the proximity gettering region.  
 
   
   
   
       14 . The structure of  claim 13 , wherein the plurality of voids are separated by a critical length (λ C ) that is dependent on the radius (R C ) of a number of holes used to form the plurality of voids using the surface transformation process.  
   
   
       15 . The structure of  claim 13 , wherein the precisely-determined arrangement of a plurality of voids is uniformly distributed through the at least one gettering region.  
   
   
       16 . The wafer of  claim 13 , wherein the plurality of precisely-formed voids includes a sphere-shaped void.  
   
   
       17 . The wafer of  claim 13 , wherein the plurality of precisely-formed voids includes a pipe-shaped void.  
   
   
       18 . The wafer of  claim 13 , wherein the plurality of precisely-formed voids includes a plate-shaped void.  
   
   
       19 . A memory device, comprising: 
 at least one gettering region formed in a semiconductor substrate, the gettering region including a precise arrangement of precisely-formed voids to getter impurities from a crystalline semiconductor region of the substrate;    a memory array formed in the crystalline semiconductor region, including a plurality of memory cells formed in rows and columns, and at least one transistor for each of the plurality of memory cells;    a plurality of word lines, each word line being connected to a row of memory cells;    a plurality of bit lines, each bit line being connected to a column of memory cells; and    control circuitry, including word line select circuitry and bit line select circuitry to select a number of memory cells for writing and reading operations.    
   
   
       20 . The device of  claim 1 , wherein the precise arrangement of the plurality of voids is uniformly distributed through the gettering region.  
   
   
       21 . The device of  claim 1 , wherein the plurality of voids are separated by a critical length (λ C ) that is dependent on a radius (R C ) of a number of holes used to form the plurality of voids using a surface transformation process.  
   
   
       22 . The device of  claim 1 , wherein each of the voids has an interior surface that includes dangling bonds such that the plurality of voids getter impurities from the at least one device region.  
   
   
       23 . The device of  claim 22 , wherein: 
 the gettering region has a volume; and    the precisely-determined arrangement of the plurality of precisely-formed voids is formed to provide a large ratio between the interior surface of the plurality of precisely-formed voids and the volume to enhance gettering of the crystalline semiconductor region.    
   
   
       24 . The wafer of  claim 1 , wherein the plurality of precisely-formed voids includes a sphere-shaped void.  
   
   
       25 . The wafer of  claim 1 , wherein the plurality of precisely-formed voids includes a pipe-shaped void.  
   
   
       26 . The wafer of  claim 1 , wherein the plurality of precisely-formed voids includes a plate-shaped void.