Polynorbornene foam insulation for integrated circuits

Abstract

Methods of providing foamed polynorbomene insulating material for use with an integrated circuit device, as well as apparatus and systems making use of such foamed polynorbomene insulating materials. The methods include forming a layer of polynorbomene material and converting at least a portion of the layer of polynorbomene material to a foamed polynorbomene material, such as by exposing the layer of polynorbomene material to a supercritical fluid. The foamed polynorbomene material can provide electrical insulation between conductive layers of the integrated circuit device.

1 . A semiconductor die, comprising: 
 an integrated circuit supported by a substrate and having a plurality of integrated circuit devices; and    two or more conductive layers coupled to the plurality of integrated circuit devices;    wherein a first conductive layer of the two or more conductive layers is electrically insulated from a second conductive layer of the two or more conductive layers by a foamed polynorbomene material.    
   
   
       2 . The semiconductor die of  claim 1 , wherein the foamed polynorbomene material has a cell size of less than about 3.0 microns.  
   
   
       3 . The semiconductor die of  claim 2 , wherein the foamed polynorbomene material comprises a foamed Avatrel™ polynorbornene material.  
   
   
       4 . The semiconductor die of  claim 1 , wherein the foamed polynorbornene material has a cell size of less than about 1.0 micron.  
   
   
       5 . The semiconductor die of  claim 1 , wherein the foamed polynorbornene material has a cell size of less than about 0.1 microns.  
   
   
       6 . The semiconductor die of  claim 1 , wherein the foamed polynorbornene material comprises a foamed Avatrel™ polynorbornene material.  
   
   
       7 . A memory device, comprising: 
 an array of memory cells;    a row access circuit coupled to the array of memory cells;    a column access circuit coupled to the array of memory cells;    an address decoder circuit coupled to the row access circuit and the column access circuit; and    two or more conductive layers coupled to one or more of the array of memory cells, the address decoder circuit, the row access circuit and the column access circuit;    wherein a first conductive layer of the two or more conductive layers is electrically insulated from a second conductive layer of the two or more conductive layers by a foamed polynorbomene material.    
   
   
       8 . The memory device of  claim 7 , wherein the foamed polynorbornene material comprises a foamed Avatrel™ polynorbornene material.  
   
   
       9 . The memory device of  claim 7 , wherein the foamed polynorbornene material has a cell size of less than about 3.0 microns.  
   
   
       10 . The memory device of  claim 7 , wherein the foamed polynorbomene material has a cell size of less than about 1.0 micron.  
   
   
       11 . The memory device of  claim 7 , wherein the foamed polynorbomene material has a cell size of less than about 0.1 microns.  
   
   
       12 . The memory device of  claim 11 , wherein the foamed polynorbomene material includes a foamed Avatrel™ polynorbornene material.  
   
   
       13 . A memory module, comprising: 
 a support;    a plurality of leads extending from the support;    a command link coupled to at least one of the plurality of leads;    a plurality of data links, wherein each data link is coupled to at least one of the plurality of leads; and    at least one memory device contained on the support and coupled to the command link, wherein the at least one memory device comprises: 
 an array of memory cells;  
 a row access circuit coupled to the array of memory cells;  
 a column access circuit coupled to the array of memory cells;  
 an address decoder circuit coupled to the row access circuit and the column access circuit; and  
 two or more conductive layers coupled to one or more of the array of memory cells, the address decoder circuit, the row access circuit and the column access circuit;  
   wherein a first conductive layer of the two or more conductive layers is electrically insulated from a second conductive layer of the two or more conductive layers by a foamed polynorbomene material.    
   
   
       14 . The memory module of  claim 13 , wherein the foamed polynorbomene material has a cell size of less than about 3.0 microns.  
   
   
       15 . The memory module of  claim 13 , wherein the foamed polynorbomene material has a cell size of less than about 0.1 microns.  
   
   
       16 . A memory system, comprising: 
 a controller;    a command link coupled to the controller;    a data link coupled to the controller; and    a memory device coupled to the command link and the data link, wherein the memory device comprises: 
 an array of memory cells;  
 a row access circuit coupled to the array of memory cells;  
 a column access circuit coupled to the array of memory cells;  
 an address decoder circuit coupled to the row access circuit and the column access circuit; and  
 two or more conductive layers coupled to one or more of the array of memory cells, the address decoder circuit, the row access circuit and the column access circuit;  
   wherein a first conductive layer of the two or more conductive layers is electrically insulated from a second conductive layer of the two or more conductive layers by a foamed polynorbomene material.    
   
   
       17 . The memory system of  claim 16 , wherein the foamed polynorbomene material has a cell size of less than about 3.0 microns.  
   
   
       18 . The memory system of  claim 16 , wherein the foamed polynorbomene material has a cell size of less than about 0.1 microns.  
   
   
       19 . An electronic system, comprising: 
 a processor; and    a circuit module having a plurality of leads coupled to the processor, and further having a semiconductor die coupled to the plurality of leads, wherein the semiconductor die comprises: 
 an integrated circuit supported by a substrate and having a plurality of integrated circuit devices; and  
 two or more conductive layers coupled to the plurality of integrated circuit devices;  
   wherein a first conductive layer of the two or more conductive layers is electrically insulated from a second conductive layer of the two or more conductive layers by a foamed polynorbomene material.    
   
   
       20 . The electronic system of  claim 19 , wherein the foamed polynorbomene material has a cell size of less than about 3.0 microns.  
   
   
       21 . The electronic system of  claim 19 , wherein the foamed polynorbomene material has a cell size of less than about 0.1 microns.