Self diagnostic and repair in matrix display panel

Abstract

A matrix access system having a plurality of columns, comprising a plurality of circuits each being adapted for selectively accessing one of said columns; an interface, communicating data with said plurality of circuits; at least one redundant circuit, adapted for selectively accessing each of said columns and communicating data with said interface; a test circuit, for comparing data communicated by a respective one of said circuits and said redundant circuit; and means for selectively logically replacing a respective circuit with said redundant circuit.

1 - 10 . (Canceled)  
   
   
       11 . A matrix access system having a plurality of columns, comprising: 
 (a) a plurality of circuits, each selectively accessing a column;    (b) an interface, communicating data with said plurality of circuits;    (c) a test circuit, for comparing an operation of a first and second of said plurality of circuits to determine an equivalence of function with respect to communicated data; and    (d) means for selectively accessing a respective column with either said first or second circuit in dependence on a compared equivalence.    
   
   
       12 . The matrix display system according to  claim 11 , wherein said plurality of circuits are disposed in a linear array, and said test circuit is provided as a set of test circuits for each respective pair of adjacent ones of the plurality of circuits.  
   
   
       13 . The matrix display system according to  claim 11 , wherein said means for selectively logically replacing a respective circuit with said redundant circuit comprises a multiplexer for selecting an output from one of a pair of adjacent ones of said plurality of circuits.  
   
   
       14 . The matrix access system according to  claim 11 , wherein each of said columns transmits a signal representative of a grayscale level of an active matrix display pixel and wherein said plurality of circuits each receive a binary data control signal and produce a pixel grayscale level control signal.  
   
   
       15 . The matrix display system according to  claim 11 , wherein said plurality of circuits are each integrated onto a common substrate with a matrix panel display device.  
   
   
       16 . The matrix display system according to  claim 11 , wherein said interface comprises a common data bus.  
   
   
       17 . The matrix display system according to  claim 11 , wherein said first and second circuits are provided logically adjacent, and said test circuit is arranged as a set of equivalent circuits, each of said set of equivalent circuits comparing an output of a logically adjacent pair of circuits.  
   
   
       18 . The matrix display system according to  claim 11 , further comprising a scan control for controlling a testing, with said test circuit, of a plurality of sets of said first and second circuits.  
   
   
       19 . A method for automatically testing and repairing a matrix access system having a plurality of columns, comprising the steps of: 
 (a) providing a plurality of circuits each being adapted for selectively accessing a column;    (b) communicating data with said plurality of circuits;    (c) comparing an operation of a first and second of said plurality of circuits to determine an equivalence of function with respect to communicated data with a test circuit; and    (e) selectively accessing a respective column with either said first or second circuit in dependence on said comparing.    
   
   
       20 . The method according to  claim 19 , wherein each of the columns transmits a signal representative of a grayscale level of an active matrix display pixel and wherein said plurality of circuits each translate a binary data control signal into the signal representative of a grayscale level for control of a respective active matrix display pixel, the plurality of circuits each being integrated onto a common substrate with a matrix panel display device.  
   
   
       21 . The method according to  claim 19 , further comprising the step of providing the communicated data through a common data bus.  
   
   
       22 . The method according to  claim 19 , wherein said first and second circuits are provided logically adjacent, and the test circuit is arranged as a set of equivalent circuits, each of the set of equivalent circuits comparing an output of a logically adjacent pair of circuits.  
   
   
       23 . The method according to  claim 18 , further comprising the step of testing an output of a plurality of first circuits with an output of a single second circuit.