Semiconductor device and data processing system

Abstract

The present invention provides a semiconductor device such as a multi-valued flash memory or the like, which is capable of shortening a processing time required to set write control information to a sense latch. The semiconductor device is capable of electrically writing multi-value information therein. Bit lines are connected to the right and left input/output terminals of a sense latch, and data latches are connected to the respective bit lines. A decoder is provided which decodes write data supplied from outside to thereby generate write control information. The write control information is latched in each of the sense latch and data latches, and the latched control information is set as information indicative of go/no-go of the application of a write voltage, which corresponds to each value in a multivalue. A write operation based on the data latched in the sense latch is first controlled, and the write control information for the sense latches are internally transferred from the data latches in turn subsequently and successively write-controlled.

1 - 23 . (cancelled)  
   
   
       24 . A nonvolatile memory device comprising: 
 a plurality of memory cells each of which is electrically erasable and electrically programmable;    a plurality of word lines each of which couples with corresponding memory cells;    a plurality of bit lines each of which couples with corresponding memory cells;    a plurality of latch circuits each of which couples with a corresponding bit line;    a first decoder circuit; and    a controller which controls programming,    wherein said first decoder circuit outputs a first signal in accordance with a first combination of inputted data, and a first latch circuit of said plurality of latch circuits receives said first signal from said first decoder circuit,    wherein said first decoder circuit outputs a second signal in accordance with a second combination of inputted data, and a second latch circuit of said plurality of latch circuits receives said second signal from said first decoder circuit,    wherein in performing a first programming, a first memory cell of said plurality of memory cells is programmed in accordance with an output of said first latch circuit and a first level program signal,    wherein in performing a second programming, a second memory cell of said plurality of memory cells is programmed in accordance with an output of said second latch circuit and a second level program signal, after said first programming is performed, and    wherein an electrical parameter of said first memory cell is different from an electrical parameter of said second memory cell in accordance with a difference between said first level program signal and said second level program signal, after said first programming and said second programming are performed.    
   
   
       25 . A nonvolatile memory device according to  claim 24 , further comprising a buffer circuit, 
 wherein said buffer circuit couples between a data terminal and said first decoder circuit for buffering data inputted from said data terminal.    
   
   
       26 . A nonvolatile memory device according to  claim 25 , 
 wherein said controller further controls verifying,    wherein after performing said first programming, a first verifying is performed for checking whether said electrical parameter of said first memory cell satisfies a parameter limit of a first level program, and    wherein said first programming is performed again when said electrical parameter of said first memory cell does not satisfy said parameter limit of said first level program.    
   
   
       27 . A nonvolatile memory device according to  claim 26 , 
 wherein after performing said second programming, a second verifying is performed for checking whether said electrical parameter of said second memory cell satisfies a parameter limit of a second level program, and    wherein said second programming is performed again when said electrical parameter of said second memory cell does not satisfy said parameter limit of said second level program.    
   
   
       28 . A nonvolatile memory device according to  claim 27 , 
 wherein the electrical parameter is threshold voltage, and    wherein a threshold voltage of said first memory cell is different from a threshold voltage of said second memory cell.    
   
   
       29 . A nonvolatile memory device according to  claim 28 , 
 wherein each memory cell has a threshold voltage within any of a plurality of threshold voltage ranges which include a first threshold voltage range, a second threshold voltage range and a third threshold voltage range,    wherein said first threshold voltage range indicates an erase state, and said second threshold voltage range and said third threshold voltage range indicate program states,    wherein said threshold voltage of said first memory cell is to be within said second threshold voltage range indicating a first program state of said program states after said first programming, and    wherein said threshold voltage of said second memory cell is to be within said third threshold voltage range indicating a second program state of said program states after said second programming.    
   
   
       30 . A nonvolatile memory device according to  claim 29 , 
 wherein said first verifying is for checking whether said threshold voltage of said first memory cell is within said second threshold voltage range or not, and    wherein said second verifying is for checking whether said threshold voltage of said second memory cell is within said third threshold voltage range or not.    
   
   
       31 . A nonvolatile memory device according to  claim 30 , 
 wherein before performing said first programming, both of said threshold voltage of said first memory cell and said threshold voltage of said second memory cell are within said first threshold voltage range.    
   
   
       32 . A nonvolatile memory device according to  claim 31 , further comprising a second decoder circuit, 
 wherein said second decoder circuit decodes an address signal received from outside and outputs a selecting signal,    wherein said first level program signal and said second level program signal are supplied to a word line selected by said selecting signal.    
   
   
       33 . A nonvolatile memory device comprising: 
 a plurality of memory cells each of which is electrically erasable and electrically programmable;    a plurality of data lines each of which couples with corresponding memory cells;    a plurality of latch circuits each of which couples with corresponding data lines;    a first decoder;    a buffer circuit; and    a controller which controls operation,    wherein said buffer circuit stores data received from outside thereof,    wherein said first decoder outputs a first signal in accordance with a first combination of data stored in said buffer circuit and a first latch circuit of said plurality of latch circuits latches a first state in accordance with said first signal,    wherein said first decoder outputs a second signal in accordance with a second combination of data stored in said buffer circuit and a second latch circuit of said plurality of latch circuits latches a second state in accordance with said second signal,    wherein in performing a first programming of a program operation after latching of said first state in said first latch circuit, a first memory cell is programmed in accordance with an output of said first latch circuit and a first level program signal,    wherein in performing a second programming of said program operation after latching of said second state in said second latch circuit, a second memory cell is programmed in accordance with an output of said second latch circuit and a second level program signal,    wherein an electrical parameter of said first memory cell is different from an electrical parameter of said second memory cell, after performing said first programming and said second programming.    
   
   
       34 . A nonvolatile memory device according to  claim 33 , 
 wherein in performing a first reading of a read operation, said first latch circuit latches said first state in accordance with said electrical parameter of said first memory cell, and said first decoder outputs said first combination of data to said buffer circuit in accordance with said first state latched in said first latch circuit, and    wherein in performing a second reading of said read operation, said second latch circuit latches said second state in accordance with said electrical parameter of said second memory cell, and said first decoder outputs said second combination of data to said buffer circuit in accordance with said second state latched in said second latch circuit.    
   
   
       35 . A nonvolatile memory device according to  claim 34 , 
 wherein each of said plurality of memory cells has any of a plurality of conditions, a first condition of said plurality of conditions indicates an erase condition, a second condition of said plurality of conditions indicates a first program condition, and a third condition of said plurality of conditions indicates a second program condition,    wherein before performing said first programming and said second programming, both of said first memory cell and said second memory cell have said first condition indicating said erase condition.    
   
   
       36 . A nonvolatile memory,device according to  claim 35 , further comprising a plurality of word lines and a second decoder, 
 wherein each of said plurality of word lines couples with corresponding memory cells, and    wherein said second decoder decodes address signals received from outside thereof for selecting one word line of said plurality of word lines.    
   
   
       37 . A nonvolatile memory device according to  claim 36 , 
 wherein said first level program signal and said second level program signal are provided via a selected word line.    
   
   
       38 . A nonvolatile memory device according to  claim 37 , 
 wherein said second reading is performed after said first reading.    
   
   
       39 . A nonvolatile memory device according to  claim 38 , 
 wherein said latching of said second state in said second latch circuit is performed after said first programming.