Thin film magnetic memory device reducing a charging time of a data line in a data read operation

Abstract

During data reading, a sense enable signal is activated to start charging of a data line prior to formation of a current path including the data line and a selected memory cell in accordance with row and column selecting operations. Charging of the data line is completed early so that it is possible to reduce a time required from start of the data reading to such a state that a passing current difference between the data lines reaches a level corresponding to storage data of the selected memory cell, and the data reading can be performed fast.

1 - 8 . (Cancelled)  
   
   
       9 . A thin film magnetic memory device comprising: 
 a plurality of memory cells each having one of first and second electric resistances corresponding to magnetically written storage data;    a reference cell having an electric resistance intermediate between said first and second electric resistances;    a first data line being electrically coupled between first and second voltages via the selected memory cell corresponding to a selected address among said plurality of memory cells during data reading;    a second data line being electrically coupled between said first and second voltages via said reference cell during said data reading;    a level control circuit provided corresponding to said first and second data lines for changing levels of said first and second data lines to predetermined levels during said data reading; and    a data read circuit for performing a data read operation in accordance with a difference between passing currents of said first and second data lines.    
   
   
       10 . The thin film magnetic memory device according to  claim 9 , further comprising: 
 a signal line for instructing voltage change of said predetermined level to said level control circuit, wherein    said level control circuit includes capacitors each arranged between said first or second data line and an internal node, and said internal node is electrically coupled to said signal line.    
   
   
       11 . The thin film magnetic memory device according to  claim 9 , further comprising: 
 a column select line for transmitting a result of column selection, wherein    said level control circuit includes capacitors each arranged between said first or second data line and an internal node, and said internal node being electrically coupled to said column select line.    
   
   
       12 . The thin film magnetic memory device according to  claim 9 , further comprising: 
 a clamp circuit provided corresponding to each of said first and second lines for maintaining voltage levels of said first and second data lines at said predetermined level during said data reading.    
   
   
       13 . The thin film magnetic memory device according to  claim 12 , wherein 
 said clamp circuit includes a diode element arranged between a predetermined voltage and said first and second data lines.    
   
   
       14 . The thin film magnetic memory device according to  claim 12 , wherein 
 said clamp circuit includes a field-effect transistor arranged between a predetermined voltage and each of said first and second data lines, and    said field-effect transistor has a gate electrically coupled to corresponding one of said first and second data lines.    
   
   
       15 . A thin film magnetic memory device comprising: 
 a plurality of memory cells arranged in rows and columns, and each having one of first and second electric resistances corresponding to magnetically written storage data;    a reference cell having an electric resistance intermediate between said first and second electric resistances;    a first data line being electrically coupled between first and second voltages via the selected memory cell corresponding to a selected address among said plurality of memory cells during data reading;    a second data line being electrically coupled between said first and second voltages via said reference cell during said data reading;    a data read circuit for performing data read operation in accordance with a difference between passing currents of said first and second data lines,    each of said first and second data lines including bit line portions arranged corresponding to the memory cell columns, respectively, and a local data line portion arranged corresponding to said data read circuit;    a gate circuit for controlling connection between said bit line portion and said local data line portion in accordance with a column select instruction; and    a precharge circuit provided corresponding to each of said memory cell columns for precharging said first and second bit lines before said data reading, and being deactivated in response to said column select instruction during said data reading.