Method and apparatus for generating gray code for any even count value to enable efficient pointer exchange mechanisms in asynchronous FIFO's

Abstract

A method and apparatus for generating Gray code for any even count value to enable efficient pointer exchange mechanisms in asynchronous FIFO's. Allowing Gray code for any range of even count values provides the benefit of decreasing metastability when exchanging pointers for FIFO buffers in asynchronous environments. Utilizing the Gray code adjacency principle, which provides that only one bit changes for any successive numbers, in a larger class of numbers than previously utilized, decreases metastability.

1 - 20 . (canceled)  
   
   
       21 . A computing appliance comprising: 
 a storage medium including executable content;    a control logic, coupled with the storage medium to selectively access and execute the content to generate Gray code for any even range of values.    
   
   
       22 . A computing system according to  claim 21 , further comprising an input port, to receive pointers for a FIFO buffer from a network device in one clock domain.  
   
   
       23 . A computing appliance according to  claim 22  further comprising an output port, coupled to a network device in a different clock domain, to send the pointers to the network device.  
   
   
       24 . A method of obtaining Gray code representations of values comprising: 
 obtaining an even range of values corresponding to a received value;    calculating an offset in accordance with the received value;    applying the offset to each value in the range; and    converting the offset values to their Gray code representations.    
   
   
       25 . The method of  claim 24 , wherein obtaining the even range of values corresponding to a received value further comprises: 
 determining a number of binary digits that represent the received value wherein a maximum value of the range is a largest value that can be represented by the number of binary digits and a minimum value of the range is a smallest value that can be represented by the number of binary digits.    
   
   
       26 . The method of  claim 25 , wherein calculating an offset in accordance with the received value further comprises: 
 determining a difference between the maximum value and the received value;    halving the difference and calculating a remainder, wherein the remainder is the offset.    
   
   
       27 . The method of  claim 24 , wherein applying the offset to each value in the range further comprises: 
 adding the offset to each value in the range.    
   
   
       28 . The method of  claim 25 , wherein the smallest value is zero.  
   
   
       29 . A method comprising: 
 receiving any integer of a range of integers, the range having a minimum integer and a maximum integer, the total numeric count of integers from the minimum integer to the maximum integer being an even, non-power-of-two number; and    representing the integer in Gray code representation.    
   
   
       30 . A method according to  claim 29 , wherein representing the integer in Gray code further comprises: 
 determining a number of binary digits required to represent the received integer;    subtracting the received integer from a maximum value represented when all the binary digits are one to result in a difference;    dividing the difference by two to result in a quotient;    adding the quotient to each numeric count from the minimum integer to the received integer to result in a series of sums; and    converting each sum to a corresponding Gray code representation.    
   
   
       31 . A method according to  claim 29 , wherein converting each sum to Gray code representation comprises performing a conversion with a binary-to-Gray converter circuit.  
   
   
       32 . A counter circuit to produce a count according to the adjacency principle of Gray code, comprising: 
 a binary counter to provide a binary integer, the binary integer selected from a range of numbers represented by a minimum number to a maximum number, the range being any even value; and    logic coupled with the binary counter to receive the binary integer and generate a representation of the binary integer according to the adjacency principle.    
   
   
       33 . A counter circuit according to  claim 32 , wherein the logic further comprises arithmetic logic to perform addition and division.  
   
   
       34 . A counter circuit according to  claim 33 , wherein the logic further comprises a exclusive OR (XOR) coupled with the arithmetic logic to bitwise XOR selective outputs of the arithmetic logic.  
   
   
       35 . A counter circuit according to  claim 32 , wherein the logic further comprises a binary-to-Gray conversion circuit.