Pr2O3-based la-oxide gate dielectrics

Abstract

A dielectric film having a layer of Pr 2 O 3 and a layer of another lanthanide oxide, and a method of fabricating such a dielectric film produce a reliable gate dielectric with a equivalent oxide thickness thinner than attainable using SiO 2 . A gate dielectric is formed as a nanolaminate of Pr 2 O 3 and a lanthanide oxide selected from the group consisting of Nd 2 O 3 , Sm 2 O 3 , Gd 2 O 3 , and Dy 2 O 3 by electron beam evaporation. These gate dielectrics having a lanthanide oxide nanolaminate are thermodynamically stable such that the nanolaminate forming the gate dielectric will have minimal reactions with a silicon substrate or other structures during processing.

1 . An electronic device comprising: 
 a substrate; and    a dielectric layer, the dielectric layer including: 
 a layer of Pr 2 O 3 ; and  
 a layer of another lanthanide oxide disposed on the layer of Pr 2 O 3 .  
   
   
   
       2 . The electronic device of  claim 1 , wherein the layer of Pr 2 O 3  and the layer of another lanthanide oxide include a nanolaminate of Pr 2 O 3  and the other lanthanide oxide.  
   
   
       3 . The electronic device of  claim 1 , wherein the layer of another lanthanide oxide includes a layer of a lanthanide oxide selected from the group consisting of Nd 2 O 3 , Sm 2 O 3 , Gd 2 O 3 , and Dy 2 O 3 .  
   
   
       4 . The electronic device of  claim 3 , wherein the dielectric layer has an effective dielectric constant ranging from about 11 to about 15.  
   
   
       5 . The electronic device of  claim 1 , wherein the dielectric layer has an effective dielectric constant ranging from a dielectric constant of Pr 2 O 3  to a dielectric constant of the other lanthanide oxide.  
   
   
       6 . The electronic device of  claim 1 , wherein the dielectric layer further includes one or more additional layers of a lanthanide oxide, each of the additional layers of lanthanide oxide selected from a group consisting of Pr 2 O 3 , Nd 2 O 3 , Sm 2 O 3 , Gd 2 O 3 , and Dy 2 O 3 .  
   
   
       7 . The electronic device of  claim 6 , wherein the dielectric layer has an equivalent oxide thickness less than or equal to about 14 Å.  
   
   
       8 . The electronic device of  claim 1 , wherein the dielectric layer is disposed in a transistor.  
   
   
       9 . The electronic device of  claim 1 , wherein the dielectric layer is disposed in a memory.  
   
   
       10 . The electronic device of  claim 1 , wherein the electronic device is configured in an electronic system.  
   
   
       11 . A transistor comprising: 
 a body region on a substrate between a first and a second source/drain regions;    a film containing Pr 2 O 3  and another lanthanide oxide on the body region between the first and second source/drain regions; and    a gate coupled to the film;    the film being formed by a method including: 
 forming a layer of Pr 2 O 3  onto the body region; and  
 forming a layer of another lanthanide oxide onto the layer of Pr 2 O 3 .  
   
   
   
       12 . The transistor of  claim 11 , wherein the film includes a nanolaminate of Pr 2 O 3  and the other lanthanide oxide.  
   
   
       13 . The transistor of  claim 11 , wherein the layer of another lanthanide oxide includes a layer of a lanthanide oxide selected from the group consisting of Nd 2 O 3 , Sm 2 O 3 , Gd 2 O 3 , and Dy 2 O 3 .  
   
   
       14 . The transistor of  claim 13 , wherein the film has an effective dielectric constant ranging from a dielectric constant of Pr 2 O 3  to a dielectric constant of the selected lanthanide oxide.  
   
   
       15 . The transistor of  claim 11 , wherein forming a layer of Pr 2 O 3  and forming a layer of another lanthanide oxide includes forming both layers by electron beam evaporation.  
   
   
       16 . A transistor comprising: 
 a body region on a substrate between a first and a second source/drain regions;    a film containing a layer of Pr 2 O 3  and a layer of another lanthanide oxide on the body region between the first and second source/drain regions; and    a gate coupled to the film.    
   
   
       17 . The transistor of  claim 16 , wherein the layer of Pr 2 O 3  and the layer of the other lanthanide oxide include a nanolaminate of Pr 2 O 3  and the other lanthanide oxide.  
   
   
       18 . The transistor of  claim 16 , wherein the layer of another lanthanide oxide includes a layer of a lanthanide oxide selected from the group consisting of Nd 2 O 3 , Sm 2 O 3 , Gd 2 O 3 , and Dy 2 O 3 .  
   
   
       19 . The transistor of  claim 18 , wherein the film has an effective dielectric constant ranging from a dielectric constant of Pr 2 O 3  to a dielectric constant of the selected lanthanide oxide.  
   
   
       20 . The transistor of  claim 18 , wherein the film further includes one or more additional layers of a lanthanide oxide, each of the additional layers of a lanthanide oxide selected from a group consisting of Pr 2 O 3 , Nd 2 O 3 , Sm 2 O 3 , Gd 2 O 3 , and Dy 2 O 3 .  
   
   
       21 . The transistor of  claim 16 , wherein the dielectric layer has an effective dielectric constant ranging from about 11 to about 15.  
   
   
       22 . The transistor of  claim 16 , wherein the dielectric layer has an equivalent oxide thickness less than or equal to about 14 Å.  
   
   
       23 . A transistor comprising: 
 a body region on a substrate between a first and a second source/drain regions;    a gate dielectric disposed on the body region;    a floating gate disposed on the gate dielectric;    a control gate; and    a floating gate dielectric interposed between the floating gate and the control gate, wherein at least one of the gate dielectric and the floating gate dielectric includes a film containing Pr 2 O 3  and another lanthanide oxide;    the film being formed by a method including: 
 forming a layer of Pr 2 O 3 ; and  
 forming a layer of another lanthanide oxide onto the layer of Pr 2 O 3 .  
   
   
   
       24 . The transistor of  claim 23 , wherein the film is configured as the gate dielectric.  
   
   
       25 . The transistor of  claim 23 , wherein the film is configured as the floating gate dielectric.  
   
   
       26 . The transistor of  claim 23 , wherein the film includes a nanolaminate of Pr 2 O 3  and the other lanthanide oxide.  
   
   
       27 . The transistor of  claim 23 , wherein the layer of another lanthanide oxide includes a layer of a lanthanide oxide selected from the group consisting of Nd 2 O 3 , Sm 2 O 3 , Gd 2 O 3 , and Dy 2 O 3 .  
   
   
       28 . The transistor of  claim 23 , wherein forming a layer of Pr 2 O 3  and forming a layer of another lanthanide oxide includes forming both layers by electron beam evaporation.  
   
   
       29 . A transistor comprising: 
 a body region on a substrate between a first and a second source/drain regions;    a gate dielectric disposed on the body region;    a floating gate disposed on the gate dielectric;    a control gate; and    a floating gate dielectric interposed between the floating gate and the control gate, wherein at least one of the gate dielectric and the floating gate dielectric includes a film containing Pr 2 O 3  and another lanthanide oxide.    
   
   
       30 . The transistor of  claim 29 , wherein the film is configured as the gate dielectric.  
   
   
       31 . The transistor of  claim 29 , wherein the film is configured as the floating gate dielectric.  
   
   
       32 . The transistor of  claim 29 , wherein the layer of Pr 2 O 3  and the layer of the other lanthanide oxide include a nanolaminate of Pr 2 O 3  and the other lanthanide oxide.  
   
   
       33 . The transistor of  claim 29 , wherein the layer of another lanthanide oxide includes a layer of a lanthanide oxide selected from the group consisting of Nd 2 O 3 , Sm 2 O 3 , Gd 2 O 3 , and Dy 2 O 3 .  
   
   
       34 . The transistor of  claim 33 , wherein the film further includes one or more additional layers of a lanthanide oxide, each of the additional layers of a lanthanide oxide selected from a group consisting of Pr 2 O 3 , Nd 2 O 3 , Sm 2 O 3 , Gd 2 O 3 , and Dy 2 O 3 .  
   
   
       35 . A memory having a memory array comprising: 
 a number of access transistors, each access transistor including a gate coupled to a film containing Pr 2 O 3  and another lanthanide oxide, the film formed on a body region on a substrate between a first and a second source/drain regions;    a number of word lines coupled to a number of the gates of the number of access transistors;    a number of source lines coupled to a number of the first source/drain regions of the number of access transistors; and    a number of bit lines coupled to a number of the second source/drain regions of the number of access transistors;    the film being formed by a method including: 
 forming a layer of Pr 2 O 3  onto the body region; and  
 forming a layer of another lanthanide oxide onto the layer of Pr 2 O 3 .  
   
   
   
       36 . The memory of  claim 35 , wherein the film includes a nanolaminate of Pr 2 O 3  and the other lanthanide oxide.  
   
   
       37 . The memory of  claim 35 , wherein the layer of another lanthanide oxide includes a layer of a lanthanide oxide selected from the group consisting of Nd2O3, Sm 2 O 3 , Gd 2 O 3 , and Dy 2 O 3 .  
   
   
       38 . The memory of  claim 37 , wherein the film has an effective dielectric constant ranging from a dielectric constant of Pr 2 O 3  to a dielectric constant of the selected lanthanide oxide.  
   
   
       39 . The memory of  claim 35 , wherein forming a layer of Pr 2 O 3  and forming a layer of another lanthanide oxide includes forming both layers by electron beam evaporation.  
   
   
       40 . A memory having a memory array comprising: 
 a number of transistors, each transistor including a gate coupled to a film containing a layer of Pr 2 O 3  and a layer of another lanthanide oxide, the film disposed above a body region on a substrate between a first and a second source/drain regions;    a number of word lines coupled to a number of the gates of the number of transistors;    a number of source lines coupled to a number of the first source/drain regions of the number of transistors; and    a number of bit lines coupled to a number of the second source/drain regions of the number of transistors.    
   
   
       41 . The memory of  claim 40 , wherein the film is configured as a floating gate dielectric and the gate is configured as a control gate.  
   
   
       42 . The memory of  claim 40 , wherein the film is configured as a gate dielectric and the gate is configured as a control gate.  
   
   
       43 . The memory of  claim 40 , wherein the layer of Pr 2 O 3  and the layer of the other lanthanide oxide include a nanolaminate of Pr 2 O 3  and the other lanthanide oxide.  
   
   
       44 . The memory of  claim 40 , wherein the layer of another lanthanide oxide includes a layer of a lanthanide oxide selected from the group consisting of Nd 2 O 3 , Sm 2 O 3 , Gd 2 O 3 , and Dy 2 O 3 .  
   
   
       45 . The memory of  claim 44 , wherein the film has an effective dielectric constant ranging from a dielectric constant of Pr 2 O 3  to a dielectric constant of the selected lanthanide oxide.  
   
   
       46 . The memory of  claim 40 , wherein the dielectric layer has an effective dielectric constant ranging from about 11 to about 15.  
   
   
       47 . The memory of  claim 40 , wherein the dielectric layer has an equivalent oxide thickness less than or equal to about 14 Å.  
   
   
       48 . The memory of  claim 40 , the film further includes one or more additional layers of a lanthanide oxide, each of the additional layers of a lanthanide oxide selected from a group consisting of Pr 2 O 3 , Nd 2 O 3 , Sm 2 O 3 , Gd 2 O 3 , and Dy 2 O 3 .  
   
   
       49 . An electronic system comprising: 
 a processor;    a memory having a memory array, the memory array including: 
 a number of access transistors, each access transistors having a gate coupled to a film containing Pr 2 O 3  and another lanthanide oxide, the film located on a body region on a substrate between a first and a second source/drain regions;  
 a number of word lines coupled to a number of the gates of the number of access transistors;  
 a number of source lines coupled to a number of the first source/drain regions of the number of access transistors;  
 a number of bit lines coupled to a number of the second source/drain regions of the number of access transistors; and  
   a system bus that couples the processor to the memory;    the film being formed by a method including: 
 forming a layer of Pr 2 O 3  onto the body region; and  
 forming a layer of another lanthanide oxide onto the layer of Pr 2 O 3 .  
   
   
   
       50 . The electronic system of  claim 49 , wherein the film includes a nanolaminate of Pr 2 O 3  and the other lanthanide oxide.  
   
   
       51 . The electronic system of  claim 49 , wherein forming a layer of another lanthanide oxide includes forming a layer of a lanthanide oxide selected from the group consisting of Nd 2 O 3 , Sm 2 O 3 , Gd 2 O 3 , and Dy 2 O 3 .  
   
   
       52 . The electronic system of  claim 51 , wherein the film has an effective dielectric constant ranging from a dielectric constant of Pr 2 O 3  to a dielectric constant of the selected lanthanide oxide.  
   
   
       53 . The electronic system of  claim 49 , wherein forming a layer of Pr 2 O 3  and forming a layer of another lanthanide oxide includes forming both layers by electron beam evaporation.  
   
   
       54 . An electronic system comprising: 
 a processor; and    a memory having a memory array, the memory array including: 
 a number of transistors, each transistors having a gate coupled to a film containing a layer of Pr 2 O 3  and a layer of another lanthanide oxide, the film disposed above a body region on a substrate between a first and a second source/drain regions;  
 a number of word lines coupled to a number of the gates of the number of transistors;  
 a number of source lines coupled to a number of the first source/drain regions of the number of transistors;  
 a number of bit lines coupled to a number of the second source/drain regions of the number of transistors; and  
   a system bus that couples the processor to the memory.    
   
   
       55 . The electronic system of  claim 54 , wherein the film is configured as a floating gate dielectric and the gate is configured as a control gate.  
   
   
       56 . The electronic system of  claim 54 , wherein the film is configured as a gate dielectric and the gate is configured as a control gate.  
   
   
       57 . The electronic system of  claim 54 , wherein the film includes a nanolaminate of Pr 2 O 3  and the other lanthanide oxide.  
   
   
       58 . The electronic system of  claim 54 , wherein forming a layer of another lanthanide oxide includes forming a layer of a lanthanide oxide selected from the group consisting of Nd 2 O 3 , Sm 2 O 3 , Gd 2 O 3 , and Dy 2 O 3 .  
   
   
       59 . The electronic system of  claim 58 , wherein the film has an effective dielectric constant ranging from a dielectric constant of Pr 2 O 3  to a dielectric constant of the selected lanthanide oxide.  
   
   
       60 . The electronic system of  claim 58 , wherein the film further includes one or more additional layers of a lanthanide oxide, each of the additional layers of a lanthanide oxide selected from a group consisting of Pr 2 O 3 , Nd 2 O 3 , Sm 2 O 3 , Gd 2 O 3 , and Dy 2 O 3 .  
   
   
       61 . The electronic system of  claim 54 , wherein the dielectric layer has an effective dielectric constant ranging from about 11 to about 15.  
   
   
       62 . The electronic system of  claim 54 , wherein the dielectric layer has an equivalent oxide thickness less than or equal to about 14 Å.