Memory utilizing oxide-nitride nanolaminates

Abstract

Structures, systems and methods for transistors utilizing oxide-nitride nanolaminates are provided. One transistor embodiment includes a first source/drain region, a second source/drain region, and a channel region therebetween. A gate is separated from the channel region by a gate insulator. The gate insulator includes oxide-nitride nanolaminate layers to trap charge in potential wells formed by different electron affinities of the oxide-nitride nanolaminate layers.

1 . A method for operating a transistor array, comprising: 
 programming one or more transistors in the array in a reverse direction, wherein each transistor includes a source region, a drain region, a channel region between the source and the drain regions, and a gate separated from the channel region by a gate insulator, wherein the gate insulator includes oxide-nitride nanolaminate layers with charge trapping in potential wells formed by different electron affinities of the oxide-nitride nanolaminate layers, wherein the array includes a number of sourcelines coupled to the source regions of each transistor along rows in the array, and wherein the array includes a number of bitlines coupled to the drain region along rows in the array, and wherein programming the one or more transistors in the reverse direction includes: 
 applying a first voltage potential to a drain region of the transistor;  
 applying a second voltage potential to a source region of the transistor;  
 applying a gate potential to a gate of the transistor; and  
 wherein applying the first, second and gate potentials to the one or more transistors includes creating a hot electron injection into the gate insulator of the one or more transistors adjacent to the source region such that the one or more transistors become programmed transistors having one of a number of charge levels trapped in the gate insulator such that the programmed transistor operates at reduced drain source current in a forward direction.  
   
   
   
       2 . The method of  claim 1 , wherein applying a first voltage potential to the drain region of the transistor includes grounding the drain region of the transistor.  
   
   
       3 . The method of  claim 2 , wherein applying a second voltage potential to the source region includes applying a high voltage potential (VDD) to a sourceline coupled thereto.  
   
   
       4 . The method of  claim 3 , wherein applying a gate potential to the gate of the transistor includes applying a gate potential to the gate in order to create a conduction channel between the source and drain regions of the transistor.  
   
   
       5 . The method of  claim 1 , wherein the method further includes reading one or more transistors in the array by operating an addressed transistor in a forward direction, wherein operating the transistor in the forward direction includes: 
 grounding the source region for the addressed transistor;    precharging the drain region for the addressed transistor to a fractional voltage of VDD; and    applying a gate potential of approximately 1.0 Volt to the gate for the addressed transistor such that a conductivity state of the addressed transistor can be compared to a conductivity state of a reference cell.    
   
   
       6 . The method of  claim 1 , wherein in creating a hot electron injection into the gate insulator of the one or more transistors adjacent to the source region includes creating a first threshold voltage region (Vt1) adjacent to the drain region and creating a second threshold voltage region (Vt2) adjacent to the source region.  
   
   
       7 . A method for multistate memory, comprising: 
 writing to one or more vertical MOSFETs arranged in rows and columns extending outwardly from a substrate and separated by trenches in a DRAM array in a reverse direction, wherein each MOSFET in the DRAM array includes a source region, a drain region, a channel region between the source and the drain regions, and a gate separated from the channel region by a gate insulator in the trenches, wherein the gate insulator includes oxide-nitride nanolaminate layers with charge trapping in potential wells formed by different electron affinities of the oxide-nitride nanolaminate layers, wherein the DRAM array includes a number of sourcelines formed in a bottom of the trenches between rows of the vertical MOSFETs and coupled to the source regions of each transistor along rows the vertical MOSFETs, wherein along columns of the vertical MOSFETs the source region of each column adjacent vertical MOSFET couple to the sourceline in a shared trench, and wherein the DRAM array includes a number of bitlines coupled to the drain region along rows in the DRAM array, and wherein programming the one or more vertical MOSFETs in the reverse direction includes; 
 biasing a sourceline for two column adjacent vertical MOSFETs sharing a trench to a voltage higher than VDD;  
 grounding a bitline coupled to one of the drain regions of the two column adjacent vertical MOSFETs in the vertical MOSFET to be programmed  
 applying a gate potential to the gate for each of the two column adjacent vertical MOSFETs to create a hot electron injection into the gate insulator of the vertical MOSFET to be programmed adjacent to the source region such that an addressed MOSFETs becomes a programmed MOSFET and will operate at reduced drain source current in a forward direction;  
   reading one or more vertical MOSFETs in the DRAM array in a forward direction, wherein reading the one or more MOSFETs in the forward direction includes; 
 grounding a sourceline for two column adjacent vertical MOSFETs sharing a trench;  
 precharging the drain regions of the two column adjacent vertical MOSFETs sharing a trench to a fractional voltage of VDD; and  
 applying a gate potential of approximately 1.0 Volt to the gate for each of the two column adjacent vertical MOSFETs sharing a trench such that a conductivity state of an addressed vertical MOSFET can be compared to a conductivity state of a reference cell.  
   
   
   
       8 . The method of  claim 7 , wherein creating a hot electron injection into the gate insulator of the addressed MOSFET adjacent to the source region includes creating a first threshold voltage region (Vt1) adjacent to the drain region and creating a second threshold voltage region (Vt2) adjacent to the source region, wherein Vt2 is greater that Vt1.  
   
   
       9 . The method of  claim 7 , wherein reading one or more vertical MOSFETs in the DRAM array in a forward direction includes using a sense amplifier to detect whether an addressed vertical MOSFET is a programmed vertical MOSFET, wherein a programmed vertical MOSFET will not conduct, and wherein an un-programmed vertical MOSFET addressed over approximately 10 ns will conduct a current of approximately 12.5 μA such that the method includes detecting an integrated drain current having a charge of 800,000 electrons using the sense amplifier.  
   
   
       10 . The method of  claim 7 , wherein in creating a hot electron injection into the gate insulator of an addressed vertical MOSFET includes changing a threshold voltage for the vertical MOSFET by approximately 0.5 Volts.  
   
   
       11 . The method of  claim 7 , wherein creating a hot electron injection into the gate insulator of the addressed vertical MOSFET includes trapping a stored charge in the gate insulator of the addressed vertical MOSFET of approximately 10 12  electrons/cm 2 .  
   
   
       12 . The method of  claim 7 , wherein creating a hot electron injection into the gate insulator of the addressed vertical MOSFET includes trapping a stored charge in the gate insulator of the addressed vertical MOSFET of approximately 100 electrons.  
   
   
       13 . The method of  claim 7 , wherein the method further includes using the vertical MOSFET as active device with gain, and wherein reading a programmed vertical MOSFET includes providing an amplification of a stored charge in the gate insulator from 100 to 800,000 electrons over a read address period of approximately 10 ns.  
   
   
       14 . A method for forming a transistor, comprising: 
 forming a first source/drain region, a second source/drain region, and a channel region therebetween in a substrate;    forming a gate insulator opposing the channel region, wherein forming the gate insulator includes forming oxide-nitride nanolaminate layers which trap charge in potential wells formed by different electron affinities of the oxide-nitride nanolaminate layers; and    forming a gate opposing the gate insulator.    
   
   
       15 . The method of  claim 14 , wherein forming oxide-nitride nanolaminate layers includes forming oxide-nitride nanolaminate layers of silicon nitride.  
   
   
       16 . The method of  claim 14 , wherein forming oxide-nitride nanolaminate layers includes forming oxide-nitride nanolaminate layers of aluminum nitride.  
   
   
       17 . The method of  claim 14 , wherein forming oxide-nitride nanolaminate layers includes forming oxide-nitride nanolaminate layers of gallium nitride.  
   
   
       18 . The method of  claim 14 , wherein forming oxide-nitride nanolaminate layers includes forming oxide-nitride nanolaminate layers of gallium aluminum nitride.  
   
   
       19 . The method of  claim 14 , wherein forming oxide-nitride nanolaminate layers includes forming oxide-nitride nanolaminate layers of tantalum aluminum nitride.  
   
   
       20 . The method of  claim 14 , wherein forming oxide-nitride nanolaminate layers includes forming oxide-nitride nanolaminate layers of titanium silicon nitride.  
   
   
       21 . The method of  claim 14 , wherein forming oxide-nitride nanolaminate layers includes forming oxide-nitride nanolaminate layers of titanium aluminum nitride.  
   
   
       22 . The method of  claim 14 , wherein forming oxide-nitride nanolaminate layers includes forming oxide-nitride nanolaminate layers of tungsten aluminum nitride.  
   
   
       23 . A method for forming a multistate memory array, comprising: 
 forming a number of vertical pillars in rows and columns extending outwardly from a substrate and separated by a number of trenches, wherein the number of vertical pillars serve as transistors including a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, and a gate separated from the channel region by a gate insulator in the trenches along rows of pillars, wherein along columns of the pillars adjacent pillars include a transistor which operates as a multistate cell on one side of a trench and a transistor which operates as a reference cell having a programmed conductivity state on the opposite side of the trench, and wherein forming the gate insulator includes forming oxide-nitride nanolaminate layers to trap charge in potential wells formed by different electron affinities of the oxide-nitride nanolaminate layers;    forming a number of bit lines coupled to the second source/drain region of each transistor along rows of the memory array;    forming a number of word lines coupled to the gate of each transistor along columns of the memory array;    forming a number of sourcelines formed in a bottom of the trenches between rows of the pillars and coupled to the first source/drain regions of each transistor along rows of pillars, wherein along columns of the pillars the first source/drain region of each transistor in column adjacent pillars couple to the sourceline in a shared trench such that a multistate cell transistor and a reference cell transistor share a common sourceline; and    wherein the number of vertical pillars can be programmed in a reverse direction to have a one of a number of charge levels trapped in the gate insulator adjacent to the first source/drain region by biasing a sourceline to a voltage higher than VDD, grounding a bitline, and selecting a gate by a wordline address.    
   
   
       24 . The method of  claim 23 , wherein forming a number of sourcelines formed in a bottom of the trenches between rows of the pillars includes implanting a doped region in the bottom of the trench.  
   
   
       25 . The method of  claim 23 , wherein, in forming a gate insulator above the channel region in the trenches along rows of pillars, the method includes forming a gate insulator having a thickness of at least 10 nanometers (nm).  
   
   
       26 . The method of  claim 23 , wherein forming oxide-nitride nanolaminate layers includes forming oxide-nitride nanolaminate layers of silicon nitride.  
   
   
       27 . The method of  claim 23 , wherein forming oxide-nitride nanolaminate layers includes forming oxide-nitride nanolaminate layers of aluminum nitride.  
   
   
       28 . The method of  claim 23 , wherein forming oxide-nitride nanolaminate layers includes forming oxide-nitride nanolaminate layers of gallium nitride.  
   
   
       29 . The method of  claim 23 , wherein forming oxide-nitride nanolaminate layers includes forming oxide-nitride nanolaminate layers of gallium aluminum nitride.  
   
   
       30 . The method of  claim 23 , wherein forming oxide-nitride nanolaminate layers includes forming oxide-nitride nanolaminate layers of tantalum aluminum nitride.  
   
   
       31 . The method of  claim 23 , wherein forming oxide-nitride nanolaminate layers includes forming oxide-nitride nanolaminate layers of titanium silicon nitride.  
   
   
       32 . The method of  claim 23 , wherein forming oxide-nitride nanolaminate layers includes forming oxide-nitride nanolaminate layers of titanium aluminum nitride.  
   
   
       33 . The method of  claim 23 , wherein forming oxide-nitride nanolaminate layers includes forming oxide-nitride nanolaminate layers of tungsten aluminum nitride.