Semiconductor device incorporating an electrical contact to an internal conductive layer and method for making the same

Abstract

A semiconductor device and its method of fabrication are provided. The semiconductor device includes a substrate, a patterning stop region, an insulating overlayer, a container region within the insulating overlayer, a charge storage lamina or conductive layer over an interior surface of the container region; a contact region defined by the charge storage lamina or conductive layer; and an electrical contact in the contact region, wherein respective portions of the electrical contact and the charge storage lamina or conductive layer occupy collectively substantially all of the container region. A bit line terminal is coupled to the charge storage lamina through a switching structure. According to one embodiment of the present invention, a central patterning stop region and a pair of lateral patterning stop regions are provided such that the container region defines a container cross section having an upper container portion and a lower container portion, wherein the lower container portion is positioned between the lateral stop regions, and wherein the upper container portion is wider than the lower container portion.

1 . A memory device comprising: 
 a storage container structure comprising: 
 a substrate including a semiconductor structure;  
 an insulating overlayer disposed over and in contact with said substrate, said insulating overlayer including a container region disposed therein, said container region defining a container cross section having container side walls, a container bottom wall, and a container interior bounded in part by said container side walls and said container bottom wall;  
 a patterning stop region disposed over said substrate such that all of said container bottom wall is defined by an upper surface of said patterning stop region;  
 a charge storage lamina over an interior surface of said container region;  
 a contact region defined by said charge storage lamina, wherein said contact region defines a contact region cross section having contact region side walls and a contact region bottom wall, and wherein said contact region side walls and said contact region bottom wall are defined by a first surface of said charge storage lamina; and  
 an electrical contact in said contact region, wherein respective portions of said electrical contact and said charge storage lamina occupy collectively at least a portion of said container region; and  
   a bit line terminal coupled to said charge storage lamina through a switching structure, wherein a charge transfer status of said switching structure changes in response to a memory access command.    
   
   
       2 . A computer system comprising: 
 a storage container structure including: 
 a substrate including a semiconductor structure;  
 an insulating overlayer disposed over and in contact with said substrate, said insulating overlayer including a container region disposed therein, said container region defining a container cross section having container side walls, a container bottom wall, and a container interior bounded in part by said container side walls and said container bottom wall;  
 a patterning stop region disposed over said substrate such that all of said container bottom wall is defined by an upper surface of said patterning stop region;  
 a charge storage lamina over an interior surface of said container region;  
 a contact region defined by said charge storage lamina, wherein said contact region defines a contact region cross section having contact region side walls and a contact region bottom wall, and wherein said contact region side walls and said contact region bottom wall are defined by a first surface of said charge storage lamina; and  
 an electrical contact in said contact region, wherein respective portions of said electrical contact and said charge storage lamina occupy collectively at least a portion of said container region;  
   a bit line terminal coupled to said charge storage lamina through a switching structure, wherein a charge transfer status of said switching structure changes in response to a memory access command; and    a microprocessor in communication with a plurality of said charge storage structures via respective ones of a plurality of said bit line terminals.    
   
   
       3 . A memory device comprising: 
 a storage container structure including: 
 a substrate including a semiconductor structure;  
 an insulating overlayer disposed over and in contact with said substrate, said insulating overlayer including a container region disposed therein, said container region defining a container cross section having container side walls, a container bottom wall, and a container interior bounded in part by said container side walls and said container bottom wall;  
 a transistor switching structure;  
 a patterning stop region disposed over said substrate such that all of said container bottom wall is defined by an upper surface of said patterning stop region, said patterning stop region forming part of said transistor switching structure;  
 a charge storage lamina over an interior surface of said container region;  
 a contact region defined by said charge storage lamina, wherein said contact region defines a contact region cross section having contact region side walls and a contact region bottom wall, and wherein said contact region side walls and said contact region bottom wall are defined by a first surface of said charge storage lamina; and  
 an electrical contact in said contact region, wherein respective portions of said electrical contact and said charge storage lamina occupy collectively at least a portion of said container region.; and  
   a bit line terminal coupled to said charge storage lamina through said switching structure, wherein a charge transfer status of said switching structure changes in response to a memory access command.