Photomask and integrated circuit manufactured by automatically eliminating design rule violations during construction of a mask layout block

Abstract

A photomask and integrated circuit manufactured by eliminating design rule violations during construction of a mask layout block are disclosed. A photomask includes a substrate and a patterned layer including at least one feature formed on at least a portion of the substrate. The feature is defined in a mask pattern file generated by analyzing a selected position for a polygon during construction of a mask layout block and determining if the selected position creates a design rule violation in the mask layout block based on a design rule from a technology file. The mask pattern file is further generated by automatically preventing the polygon from being placed in the mask layout block at the selected position if the design rule violation exists.

1 . A photomask, comprising: 
 a substrate; and    a patterned layer including at least one feature formed on at least a portion of the substrate, the feature defined in a mask pattern file generated by:    analyzing a selected position for a polygon during construction of a mask layout block;    determining if the selected position creates a design rule violation in the mask layout block based on a design rule from a technology file; and    automatically preventing the polygon from being placed in the mask layout block at the selected position if the design rule violation exists.    
   
   
       2 . The photomask of  claim 1 , further comprising the mask pattern file generated by automatically placing the polygon in an original position in the mask layout block if the design rule violation exists.  
   
   
       3 . The photomask of  claim 1 , further comprising the mask pattern file generated by automatically adjusting the selected position until a feature dimension associated with the polygon is approximately equal to the design rule if the design rule violation exists.  
   
   
       4 . The photomask of  claim 1 , further comprising the patterned layer generated by: 
 providing a hint area in the mask layout block proximate the selected position for the polygon; and    identifying the design rule violation if the selected position for the polygon is located inside of the hint area.    
   
   
       5 . The photomask of  claim 1 , further comprising the patterned layer generated by: 
 providing a hint area in the mask layout block proximate the selected position for the polygon; and    identifying the design rule violation if the selected position for the polygon is located outside of the hint area.    
   
   
       6 . The photomask of  claim 1 , further comprising the patterned layer generated by: 
 identifying the design rule violation in at least one instance of a plurality of subcells located in a top-level cell if the selected position for the polygon creates a feature dimension less than the design rule; and    simultaneously preventing the polygon from being placed in mask layout block at the selected position in each instance of the subcell if the design rule violation is identified.    
   
   
       7 . The photomask of  claim 1 , further comprising the mask pattern file generated by: 
 determining if a feature dimension associated with the polygon is greater than the design rule; and    compacting the mask layout block by modifying the selected position until the feature dimension is approximately equal to the design rule.    
   
   
       8 . The photomask of  claim 1 , further comprising the mask pattern file generated by maintaining connectivity of a node associated with the polygon by adding an extra polygon to the mask layout block proximate a portion of the node.  
   
   
       9 . The photomask of  claim 1 , further comprising the mask pattern file generated by maintaining connectivity of a node associated with the polygon by removing at least a portion of one of a plurality of polygons associated with the node.  
   
   
       10 . A photomask assembly, comprising: 
 a pellicle assembly defined in part by a pellicle frame and a pellicle film attached thereto; and    a photomask coupled to the pellicle assembly opposite from the pellicle film, the photomask including a patterned layer including at least one feature formed on at least a portion of a substrate, the feature defined in a mask pattern file generated by: 
 analyzing a selected position for a polygon during construction of a mask layout block;  
 determining if the selected position creates a design rule violation in the mask layout block based on a design rule from a technology file; and  
 automatically preventing the polygon from being placed in the mask layout block at the selected position if the design rule violation exists.  
   
   
   
       11 . The photomask assembly of  claim 10 , further comprising the mask pattern file generated by automatically placing the polygon in an original position in the mask layout block if the design rule violation exists.  
   
   
       12 . The photomask assembly of  claim 10 , further comprising the mask pattern file generated by automatically adjusting the selected position until a feature dimension associated with the polygon is approximately equal to the design rule if the design rule violation exists.  
   
   
       13 . The photomask assembly of  claim 10 , further comprising the patterned layer generated by: 
 providing a hint area in the mask layout block proximate the selected position for the polygon; and    identifying the design rule violation if the selected position for the polygon is located inside of the hint area.    
   
   
       14 . The photomask assembly of  claim 10 , further comprising the patterned layer generated by: 
 providing a hint area in the mask layout block proximate the selected position for the polygon; and    identifying the design rule violation if the selected position for the polygon is located outside of the hint area.    
   
   
       15 . The photomask assembly of  claim 10 , further comprising the mask pattern file generated by providing a compaction area in the mask layout block proximate the selected position for the polygon, the compaction area provided to graphically represent that the feature dimension is greater than at least one of the design rules.  
   
   
       16 . An integrated circuit formed on a semiconductor wafer, comprising: 
 a plurality of interconnect layers; and    a plurality of contact layers operable to provide electrical connections between the interconnect layers;    the interconnect and contact layers formed on a semiconductor wafer using a plurality of photomasks, each photomask including a patterned layer having at least one feature defined in a mask pattern file generated by:    analyzing a selected position for a polygon during construction of a mask layout block;    determining if the selected position creates a design rule violation in the mask layout block based on a design rule from a technology file; and    automatically preventing the polygon from being placed in the mask layout block at the selected position if the design rule violation exists.    
   
   
       17 . The integrated circuit of  claim 16 , further comprising the mask pattern file generated by automatically placing the polygon in an original position in the mask layout block if the design rule violation exists.  
   
   
       18 . The integrated circuit of  claim 16 , further comprising the mask pattern file generated by automatically adjusting the selected position until a feature dimension associated with the polygon is approximately equal to the design rule if the design rule violation exists.  
   
   
       19 . The integrated circuit of  claim 16 , further comprising the patterned layer generated by: 
 providing a hint area in the mask layout block proximate the selected position for the polygon; and    identifying the design rule violation if the selected position for the polygon is located inside of the hint area.    
   
   
       20 . The integrated circuit of  claim 16 , further comprising the patterned layer generated by: 
 providing a hint area in the mask layout block proximate the selected position for the polygon; and    identifying the design rule violation if the selected position for the polygon is located outside of the hint area.    
   
   
       21 . The integrated circuit of  claim 16 , further comprising the mask pattern file generated by: 
 determining if a feature dimension associated with the polygon is greater than the design rule; and    compacting the mask layout block by modifying the selected position until the feature dimension is approximately equal to the design rule.    
   
   
       22 . The integrated circuit of  claim 16 , further comprising the mask pattern file generated by maintaining connectivity of a node associated with the polygon.  
   
   
       23 . The integrated circuit of  claim 16 , wherein the mask layout file comprises a hierarchical design.