Method of depositing a diffusion barrier layer and a metal conductive layer

Abstract

We disclose a method of applying a sculptured layer of material on a semiconductor feature surface using ion deposition sputtering, wherein a surface onto which the sculptured layer is applied is protected to resist erosion and contamination by impacting ions of a depositing layer, said method comprising the steps of: a) applying a first portion of a sculptured layer with sufficiently low substrate bias that a surface onto which said sculptured layer is applied is not eroded away or contaminated in an amount which is harmful to said semiconductor device performance or longevity; and b) applying a subsequent portion of said sculptured layer with sufficiently high substrate bias to sculpture a shape from said the first portion, while depositing additional layer material. The method is particularly applicable to the sculpturing of barrier layers, wetting layers, and conductive layers upon semiconductor feature surfaces and is especially helpful when the conductive layer is copper. In the application of a barrier layer, a first portion of barrier layer material is deposited on the substrate surface using standard sputtering techniques or using all ion deposition plasma, but in combination with sufficiently low substrate bias voltage (including at no applied substrate voltage) that the surfaces impacted by ions are not sputtered in an amount which is harmful to device performance or longevity. Subsequently, a second portion of barrier material is applied using ion deposition sputtering at increased substrate bias voltage which causes resputtering (sculpturing) or the first portion of barrier layer material, while enabling a more anisotropic deposition of newly depositing material. A conductive material, and particularly a copper seed layer applied to the feature may be accomplished using the same sculpturing technique as that described above with reference to the barrier layer.

1 - 30 . (Cancelled)  
   
   
       31 . A method for depositing a diffusion barrier and a metal conductive layer for metal interconnects on a wafer substrate, the method comprising: 
 (a) depositing a first portion of the diffusion barrier over the surface of the wafer substrate;    (b) etching the first portion of the diffusion barrier at the bottom of a plurality of vias without fully etching through such that an amount of barrier material remains at the bottom of the plurality of vias, while depositing a second portion of the diffusion barrier elsewhere on the wafer substrate; and    (c) depositing the metal conductive layer over the surface of the wafer substrate such that the metal conductive layer contacts the barrier material remaining at the bottom of the plurality of vias; wherein at least part of (a) and all of (b) are performed in the same processing chamber.    
   
   
       32 . The method of  claim 31 , wherein the metal conductive layer comprises copper.  
   
   
       33 . The method of  claim 31 , wherein the metal conductive layer is a seed layer.  
   
   
       34 . The method of  claim 31 , wherein the first portion of the diffusion barrier is a monolayer and the second portion of the diffusion barrier comprises a sputtered metal.  
   
   
       35 . The method of  claim 34 , wherein the sputtered metal is tantalum.  
   
   
       36 . The method of  claim 35 , wherein the monolayer comprises at least one of tantalum and tantalum nitride.  
   
   
       37 . The method of  claim 35 , wherein the monolayer comprises titanium silicon nitride.  
   
   
       38 . The method of  claim 36 , further comprising precleaning the wafer substrate prior to (a).  
   
   
       39 . The method of  claim 37 , further comprising precleaning the wafer substrate prior to (a).  
   
   
       40 . The method of  claim 31 , wherein the first portion of the diffusion barrier is a bilayer having a first deposited layer and a second deposited layer thereon, and the second portion of the diffusion barrier comprises a sputtered metal.  
   
   
       41 . The method of  claim 40 , wherein the sputtered metal is tantalum.  
   
   
       42 . The method of  claim 41 , wherein the first deposited layer comprises at least one of tantalum, nitrogen-doped tantalum, and tantalum nitride, and the second deposited layer comprises titanium silicon nitride.  
   
   
       43 . The method of  claim 41 , wherein the first deposited layer comprises titanium silicon nitride, and the second deposited layer comprises at least one of tantalum, nitrogen-doped tantalum, and tantalum nitride.  
   
   
       44 . The method of  claim 42 , further comprising precleaning the wafer substrate prior to (a).  
   
   
       45 . The method of  claim 43 , further comprising precleaning the wafer substrate prior to (a).  
   
   
       46 . The method of  claim 31 , further comprising precleaning the wafer substrate prior to (a).  
   
   
       47 . The method of  claim 31 , wherein (b) comprises a PVD etch/deposition process in which an RF frequency is applied to the wafer substrate such that the etch to deposition ratio is greater than 1 in the bottom of the plurality of vias and less than 1 on the field.  
   
   
       48 . The method of  claim 31 , wherein (b) comprises a PVD etch/deposition process in which an RF frequency is applied to the wafer substrate such that the etch rate at the bottom of the plurality of vias is greater than the etch rate on any associated horizontal trench surfaces or the field.  
   
   
       49 . The method of  claim 47 , wherein the RF frequency is between about 100 kHz and 60 MHz.  
   
   
       50 . The method of  claim 48 , wherein the RF frequency is between about 100 kHz and 60 MHz.  
   
   
       51 . The method of  claim 49 , further comprising using a source power of between about 0.5 and 8 kW.  
   
   
       52 . The method of  claim 50 , further comprising using a source power of between about 0.5 and 8 kW.  
   
   
       53 . The method of  claim 51 , further comprising using an RF power of 250 W.  
   
   
       54 . The method of  claim 52 , further comprising using an RF power of 250 W.  
   
   
       55 . The method of  claim 53 , further comprising using an Ar flow of about 10 to 45 SCCM.  
   
   
       56 . The method of  claim 54 , further comprising using an Ar flow of about 10 to 45 SCCM.  
   
   
       57 . The method of  claim 55 , further comprising using a pressure of more than 10 mTorr.  
   
   
       58 . The method of  claim 56 , further comprising using a pressure of more than 10 mTorr.  
   
   
       59 . The method of  claim 31 , wherein the method comprises a component of a Damascene process.  
   
   
       60 . The method of  claim 31 , wherein (a)-(c) are performed in the same processing tool.  
   
   
       61 . The method of  claim 38 , wherein (a)-(c) and precleaning the wafer substrate are performed in the same processing tool.  
   
   
       62 . The method of  claim 44 , wherein (a)-(c) and precleaning the wafer substrate are performed in the same processing tool.  
   
   
       63 . The method of  claim 45 , wherein (a)-(c) and precleaning the wafer substrate are performed in the same processing tool.  
   
   
       64 . The method of  claim 46 , wherein (a)-(c) and precleaning the wafer substrate are performed in the same processing tool.  
   
   
       65 . The method of  claim 31 , wherein at least one of the plurality of vias is an unlanded via.  
   
   
       66 . A method for depositing a diffusion barrier and a metal conductive layer for metal interconnects on a wafer substrate, the method comprising: 
 (a) precleaning the wafer substrate;    (b) depositing a first portion of the diffusion barrier over the surface of the wafer substrate;    (c) etching part-way through the first portion of the diffusion barrier at the bottom of a plurality of vias while depositing a second portion of the diffusion barrier elsewhere on the wafer substrate such that the diffusion barrier has a minimum thickness at the bottom of the plurality of vias; and    (d) depositing the metal conductive layer over the surface of the wafer substrate, including the minimum thickness of diffusion barrier at the bottom of the plurality of vias; wherein at least part of (b) and all of (c) are performed in the same processing chamber.    
   
   
       67 . The method of  claim 66 , wherein the metal conductive layer comprises copper.  
   
   
       68 . The method of  claim 66 , wherein the metal conductive layer is a seed layer.  
   
   
       69 . The method of  claim 66 , wherein the first portion of the diffusion barrier is a monolayer and the second portion of the diffusion barrier comprises a sputtered metal.  
   
   
       70 . The method of  claim 69 , wherein the sputtered metal is tantalum.  
   
   
       71 . The method of  claim 70 , wherein the monolayer comprises at least one of tantalum, tantalum nitride, and titanium silicon nitride.  
   
   
       72 . The method of  claim 66 , wherein the first portion of the diffusion barrier is a bilayer having a first deposited layer and a second deposited layer thereon, and the second portion of the diffusion barrier comprises a sputtered metal.  
   
   
       73 . The method of  claim 72 , wherein the sputtered metal is tantalum.  
   
   
       74 . The method of  claim 72 , wherein the first deposited layer comprises at least one of tantalum, nitrogen-doped tantalum, and tantalum nitride, and the second deposited layer comprises titanium silicon nitride.  
   
   
       75 . The method of  claim 72 , wherein the first deposited layer comprises titanium silicon nitride and the second deposited layer comprises at least one of tantalum, nitrogen-doped tantalum, and tantalum nitride.  
   
   
       76 . The method of  claim 66 , wherein (b) comprises a PVD etch/deposition process in which an RF frequency is applied to the wafer substrate such that the etch to deposition ratio is greater than 1 in the bottom of the plurality of vias and less than 1 on the field.  
   
   
       77 . The method of  claim 76 , wherein the RF frequency is between about 100 kHz and 60 MHz.  
   
   
       78 . The method of  claim 76 , wherein the RF frequency is about 13.56 MHz.  
   
   
       79 . The method of  claim 76 , further comprising using a source power of between about 0.5 and 8 kW.  
   
   
       80 . The method of  claim 79 , further comprising using an RF power of about 250 W.  
   
   
       81 . The method of  claim 80 , further comprising using an Ar flow of about 10 to 45 SCCM.  
   
   
       82 . The method of  claim 81 , further comprising using a pressure greater than 10 mTorr.  
   
   
       83 . The method of  claim 66 , wherein the method comprises a component of a Damascene process.  
   
   
       84 . The method of  claim 66 , wherein (a)-(d) are performed in the same processing tool.  
   
   
       85 . The method of  claim 49 , further comprising using a source power of 2 kW.  
   
   
       86 . The method of  claim 50 , further comprising using a source power of 2 kW.  
   
   
       87 . The method of  claim 76 , further comprising using a source power of 2 kW.  
   
   
       88 . The method of  claim 55 , further comprising using a pressure of about 40 mTorr.  
   
   
       89 . The method of  claim 56 , further comprising using a pressure of about 40 mTorr.  
   
   
       90 . The method of  claim 81 , further comprising using a pressure of about 40 mTorr.