Flexible tape electronics packaging and methods of manufacture

Abstract

To decrease the weight and the thickness, and to increase the flexibility, of an electronics package, the package includes an integrated circuit (IC) mounted on a flexible tape substrate. In an embodiment, an IC is mounted on a flexible tape substrate using a ball grid array arrangement; however, other arrangements, including lead bonding, can be used. The flexible tape substrate can comprise conductive traces, vias, and patterns of lands on one or more layers. Methods of fabrication, as well as application of the flexible tape package to an electronic assembly, an electronic system, and a data processing system, are also described.

1 . A substrate comprising: 
 a film including a conductor region to mount an integrated circuit and further including at least one sprocket hole outside the conductor region;    a plurality of traces within the film, including within the conductor region; and    a plurality of lands on a surface of the film and coupled to the traces, wherein the lands are to mount corresponding pads of the integrated circuit, the plurality of lands including a plurality of signal lands around the periphery of the conductor region, the plurality of lands further including a plurality of power and ground lands within a central core region of the conductor region.    
   
   
       2 . The substrate recited in  claim 1 , wherein the film is formed of material selected from the group consisting of polymeric film, polyimide, polyester, polyparabanic acid, epoxy, and fiberglass.  
   
   
       3 . The substrate recited in  claim 1 , wherein the pads and/or lands are arranged in a ball grid array.  
   
   
       4 . The substrate recited in  claim 1 , wherein the film comprises a plurality of contiguous layers, selected ones of which comprise a plurality of traces.  
   
   
       5 . A package substrate comprising: 
 a film including a conductor region to mount an integrated circuit;    a plurality of traces, at least some of which are within the conductor region; and    a plurality of lands on a surface of the film and coupled to the traces, wherein the lands are to mount corresponding pads of the integrated circuit, the plurality of lands including a plurality of signal lands around the periphery of the conductor region, the plurality of lands further including a plurality of power and ground lands within a central core region of the conductor region.    
   
   
       6 . The package substrate recited in  claim 5 , wherein the film is formed of material selected from the group consisting of a polymeric film, polyimide, polyester, polyparabanic acid, epoxy, and fiberglass.  
   
   
       7 . The package substrate recited in  claim 5 , wherein the film comprises a plurality of layers, each of the layers comprising a plurality of traces.  
   
   
       8 . The package substrate recited in  claim 5 , wherein the film comprises a plurality of contiguous layers, selected ones of which comprise a plurality of traces.  
   
   
       9 . An electronic package comprising: 
 a substrate including 
 a film including a conductor region to mount an integrated circuit;  
 a plurality of traces, at least some of which are within the conductor region;  
 a plurality of lands on a surface of the film and coupled to the traces, the plurality of lands including a plurality of signal lands around the periphery of the conductor region, the plurality of lands further including a plurality of power and ground lands within a central core region of the conductor region; and  
   an integrated circuit including a plurality of pads coupled to the plurality of lands in a ball grid array.    
   
   
       10 . The electronic package recited in  claim 9 , wherein the film is formed of material selected from the group consisting of a polymeric film, polyimide, polyester, polyparabanic acid, epoxy, and fiberglass.  
   
   
       11 . The electronic package recited in  claim 9 , wherein the film comprises a plurality of layers, each of the layers comprising a plurality of traces in the conductor region, and wherein each layer has a thickness within the range of approximately 0.15 to 0.30 millimeters.  
   
   
       12 . The electronic package recited in  claim 9 , wherein the film comprises a plurality of contiguous layers, selected ones of which comprise selected ones of the plurality of traces.  
   
   
       13 . An electronic system including at least one electronic assembly comprising: 
 a film including a conductor region, a plurality of traces in the conductor region, and a plurality of lands formed directly upon a surface of the film and coupled to the traces, the plurality of lands including a plurality of signal lands around the periphery of the conductor region, the plurality of lands further including a plurality of power and ground lands within a central core region of the conductor region;    an integrated circuit including a plurality of pads coupled to the plurality of lands; and    wherein the film comprises a plurality of contiguous layers, selected ones of which comprise a plurality of traces in the conductor region.    
   
   
       14 . The electronic system recited in  claim 13 , wherein the film is formed of material selected from the group consisting of a polymeric film, polyimide, polyester, polyparabanic acid, epoxy, and fiberglass.  
   
   
       15 . The electronic system recited in  claim 13 , wherein the pads and/or lands are arranged in a ball grid array.  
   
   
       16 . A data processing system comprising: 
 a bus coupling components in the data processing system;    a display coupled to the bus;    a memory coupled to the bus; and    a processor coupled to the bus and comprising an electronic assembly including, 
 a film including a conductor region, a plurality of traces in the conductor region, and a plurality of lands formed directly upon a surface of the film and coupled to the traces, the plurality of lands including a plurality of signal lands around the periphery of the conductor region, the plurality of lands further including a plurality of power and ground lands within a central core region of the conductor region; and  
 an integrated circuit including a plurality of pads coupled to the plurality of lands.  
   
   
   
       17 . The data processing system recited in  claim 16 , wherein the film is formed of material selected from the group consisting of a polymeric film, polyimide, polyester, polyparabanic acid, epoxy, and fiberglass.  
   
   
       18 . The data processing system recited in  claim 16 , wherein the film comprises a plurality of layers, each of the layers comprising a plurality of traces in the conductor region.  
   
   
       19 . The data processing system recited in  claim 16 , wherein the pads and/or lands are arranged in a ball grid array.  
   
   
       20 . A method comprising: 
 forming a film including a conductor region to mount an integrated circuit;    forming a plurality of traces, at least some of which are within the conductor region; and    forming a plurality of lands coupled to the traces, wherein the lands are to mount corresponding pads of the integrated circuit, wherein the plurality of lands include a plurality of signal lands around the periphery of the conductor region, and wherein the plurality of lands further include a plurality of power and ground lands within a central core region of the conductor region.    
   
   
       21 . The method recited in  claim 20 , wherein the substrate is formed of material selected from the group consisting of a polymeric film, polyimide, polyester, polyparabanic acid, epoxy, and fiberglass.  
   
   
       22 . The method recited in  claim 20 , wherein forming the substrate comprises forming a plurality of contiguous layers, selected ones of which comprise a plurality of traces in the conductor region.  
   
   
       23 . The method recited in  claim 20 , wherein forming the substrate comprises forming a plurality of sprocket holes outside the conductor region.  
   
   
       24 . The method recited in  claim 20 , wherein the lands are arranged in a ball grid array, the method further comprising: 
 forming solder balls on the plurality of lands.    
   
   
       25 . A method comprising: 
 forming a thin, flexible substrate including a conductor region having a plurality of traces and further having a plurality of lands coupled to the plurality of traces, wherein the plurality of lands include a plurality of signal lands around the periphery of the conductor region, and wherein the plurality of lands further include a plurality of power and ground lands within a central core region of the conductor region; and    coupling pads on an integrated circuit (IC) to corresponding lands on the substrate.    
   
   
       26 . The method recited in  claim 25 , wherein the substrate is formed of material selected from the group consisting of a polymeric film, polyimide, polyester, polyparabanic acid, epoxy, and fiberglass.  
   
   
       27 . The method recited in  claim 25 , wherein forming the substrate comprises forming a plurality of layers, selected ones of which comprise a plurality of traces in the conductor region.  
   
   
       28 . The method recited in  claim 25 , wherein forming the substrate comprises forming a plurality of sprocket holes outside the conductor region.  
   
   
       29 . The method recited in  claim 25  and further comprising before coupling: 
 forming solder balls on the lands.    
   
   
       30 . The method recited in  claim 25  and further comprising: 
 mounting the substrate on an additional substrate.    
   
   
       31 . The method recited in  claim 30 , wherein the additional substrate comprises a printed circuit board.  
   
   
       32 . The method recited in  claim 30  and further comprising before mounting: 
 forming solder balls on the lands.    
   
   
       33 . The method recited in  claim 30 , wherein lands are coupled to corresponding terminals on the additional substrate.  
   
   
       34 . The method recited in  claim 33 , wherein the lands are coupled to the terminals using a ball grid array.  
   
   
       35 . The method recited in  claim 33 , wherein leads are coupled between corresponding lands and terminals.