Semiconductor device and semiconductor substrate

Abstract

In order to provide a semiconductor device having a field effect transistor with a low power consumption and a high speed by use of the combination of Si and an element such as Ge, C or the like of the same group as Si, a strain is applied by a strain applying semiconductor layer 2 to a channel forming layer 1 having a channel of the field effect transistor formed therein so that the mobility of carriers in the channel is made larger than the mobility of carriers in that material of the channel forming layer which is unstrained.

1 - 28 . (Canceled)  
   
   
       29 . A semiconductor device forming method comprising the steps of: 
 forming an Si 1-x Ge x  strain applying layer on a semiconductor substrate, where 0<x<1;    growing a strained Si layer on said Si 1-x Ge x  strain applying layer thereby to provide in-plane tensile strain between said strained Si layer and said Si 1-x Ge x  strain applying layer;    subjecting a surface of said strained Si layer to thermal oxidation;    bonding said surface of said strained Si layer and a supporting substrate to each other;    separating at least a part of said Si 1-x Ge x  strain applying layer and at most said Si 1-x Ge x  strain applying layer and a part of said strained Si layer at a separating position; and    forming a source and drain regions of a p-MOS and n-MOS transistors within said separating position.    
   
   
       30 . A semiconductor device forming method according to  claim 29 , wherein in-plane lattice constant of said strained Si layer is larger than that of unstrained Si by a proportion less than 4%.  
   
   
       31 . A semiconductor device forming method according to  claim 30 , further comprising a step of epitaxially growing an additional strained Si layer on a surface of said Si 1-x Ge x  strain applying layer.  
   
   
       32 . A semiconductor device forming method according to  claim 29 , wherein active regions of p-MOS and n-MOS transistors are formed where an in-plane lattice constant of said strained Si layer is larger than that of unstrained Si by a proportion less than 4%.  
   
   
       33 . A semiconductor device forming method according to  claim 32 , wherein surface orientation of each of said Si 1-x Ge x  strain applying layer and said strained Si layer is {100}.  
   
   
       34 . A semiconductor device forming method according to  claim 32 , wherein the surface orientation of each of said Si 1-x Ge x  strain applying layer and said strained Si layer is {110}.  
   
   
       35 . A semiconductor device having p-MOS and n-MOS transistors, manufactured by forming an Si 1-x Ge x  strain applying layer on a semiconductor substrate, where 0<x<1; growing a strained Si layer on said Si 1-x Ge x  strain applying layer thereby to provide in-plane tensile strain between said strained Si layer and said Si 1-x Ge x  strain applying layer; subjecting a surface of said strained Si layer to thermal oxidation; bonding said surface of said strained Si layer and a supporting substrate to each other; separating at least a part of said Si 1-x Ge x  strain applying layer and at most said Si 1-x Ge x  strain applying layer and a part of said strained Si layer at a separating position; and forming a source and drain regions of p-MOS and n-MOS transistors within said separating position.  
   
   
       36 . A semiconductor device according to  claim 35 , wherein in-plane lattice constant of said Si layer is larger than that of unstrained Si by a proportion of less than 4%.  
   
   
       37 . A semiconductor device according to  claim 35 , wherein the surface orientation of each of said Si 1-x Ge x  strain applying layer and said strained Si layer is {110} and wherein an in-plane lattice constant of said strained Si layer is larger than that of unstrained Si by a proportion of less than 4%.  
   
   
       38 . A semiconductor device according to  claim 35 , wherein channel regions of p-MOS and n-MOS transistors are formed where an in-plane lattice constant of said strained Si layer is larger than that of unstrained Si by a proportion of less than 4%.