Non-volatile multi-level, semiconductor flash memory device and method of driving same

Abstract

In a nonvolatile semiconductor memory device in which a plurality of threshold values are set to store multi-level data in a memory cell, bits of multi-bit data are separately written into a memory cell according to an address signal or a control signal to effect the reading and erasing. Concretely, the memory array is so constituted that it can be accessed by three-dimensional address of X, Y and Z, and multi-bit data in the memory cell is discriminated by the Z-address.

1 . A nonvolatile memory comprising: 
 a plurality of memory cells; and    a plurality of word lines, each of which is coupled to corresponding ones of said memory cells,    wherein said nonvolatile memory is capable of receiving a plurality of commands which includes a write command accompanied with write address information,    wherein, when said nonvolatile memory receives said write command accompanied with first address information as said write address information and first data, said nonvolatile memory selects a first word line according to said first address information, and stores said first data in said memory cells coupled to said first word line,    wherein, when said nonvolatile memory receives said write command accompanied with second address information as said write address information and second data, said nonvolatile memory selects said first word line according to said second address information, further storing said second data in said memory cells coupled to said first word line,    wherein, after storing said first data, each of said memory cells coupled to said first word line has one state of a first state or a second state, and    wherein, after storing said second data, each of said memory cells coupled to said first word line has one state of said first state, said second state, a third state or a fourth state.    
   
   
       2 . A nonvolatile memory according to  claim 1 , 
 wherein a memory cell coupled to said first word line has one state of said first state or said second state according to data of said first data to be stored,    wherein said memory cell coupled to said first word line has one state of said first state or said third state according to data of said second data to be stored, when said memory cell has said first state after storing data of said first data to be stored, and    wherein said memory cell coupled to said first word line has one state of said second state or said fourth state according to data of said second data to be stored, when said memory cell has said second state after storing data of said first data to be stored.    
   
   
       3 . A nonvolatile memory according to  claim 2 , 
 wherein said commands further include a read command accompanied with read address information,    wherein, when said nonvolatile memory receives said read command accompanied with said first address information as said read address information, said nonvolatile memory selects said first word line according to said first address information, and outputs said first data stored in said memory cells coupled to said first word line, and    wherein, when said nonvolatile memory receives said read command accompanied with said second address information as said read address information, said nonvolatile memory selects said first word line according to said second address information, and outputs said second data stored in said memory cells coupled to said first word line.    
   
   
       4 . A nonvolatile memory according to  claim 2 , 
 wherein said commands further include an erase command accompanied with an erase address information,    wherein, when said nonvolatile memory receives said erase command accompanied with said first address information as said erase address information, said nonvolatile memory selects said first word line according to said first address information, erases said first data stored in said memory cells coupled to said first word line but does not erase said second data stored in said memory cells coupled to said first word line, and    wherein, when said nonvolatile memory receives said erase command accompanied with said second address information as said erase address information, said nonvolatile memory selects said first word line according to said first address information, erases said second data stored in said memory cells coupled to said first word line but does not erase said first data stored in said memory cells coupled to said first word line.